Revert "rockchip: rk3399: enable sdhci clk for emmc"
This reverts commit 462e1413
("rockchip: rk3399: enable sdhci clk
for emmc")
Enabling this clock in coreboot is no longer needed as it's handled
in the kernel driver now.
BUG=chrome-os-partner:52873
TEST=boot from usb/sdcard and check there is /dev/mmcblk0
BRANCH=none
Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0
Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/367421
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16152
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
parent
e4cc4733eb
commit
5fa08f3c0f
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@ -22,7 +22,6 @@
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#include <soc/bl31_plat_params.h>
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#include <soc/clock.h>
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#include <soc/display.h>
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#include <soc/emmc.h>
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#include <soc/grf.h>
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#include <soc/i2c.h>
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#include <soc/usb.h>
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@ -42,8 +41,6 @@ static void configure_emmc(void)
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write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
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rkclk_configure_emmc();
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enable_emmc_clk();
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}
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static void register_reset_to_bl31(void)
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@ -65,7 +65,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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ramstage-y += clock.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c
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ramstage-y += emmc.c
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ramstage-y += ../common/gpio.c
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ramstage-y += gpio.c
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ramstage-y += ../common/i2c.c
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@ -1,50 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/emmc.h>
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#define SDHCI_CLOCK_CONTROL 0x2c
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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/* TODO(crosbug.com/p/52873): We actually don't need to set clk for
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* emmc once kernel fix it's bug.
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*/
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void enable_emmc_clk(void)
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{
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int timeout, clk;
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write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), SDHCI_CLOCK_INT_EN);
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/* Wait max 20 ms */
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timeout = 20;
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while (!((clk = read32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL)))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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printk(BIOS_ERR, "Internal clock never stabilised.\n");
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), clk);
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}
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@ -1,16 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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void enable_emmc_clk(void);
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