cpu/amd: Fix cbtypes.h to match UINTN convention

There are some inconsistencies in AMDs APIs between the coreboot
code and the vendorcode code. Unify the API.

UINTN maps to uintptr_t in UEFI land. Do the same
here. Also switch the other UEFI types to map to
fixed size types.

Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/include/cpu/amd/common/cbtypes.h

@@ -20,16 +20,20 @@
 #ifndef _CBTYPES_H_
 #define _CBTYPES_H_
 
-typedef signed long long __int64;
+/* Map coreboot stdint types to AGESA types. */
+
+#include <stdint.h>
+
+typedef int64_t __int64;
 typedef void VOID;
-typedef unsigned int UINTN;
+typedef uintptr_t UINTN;
-typedef signed char CHAR8;
+typedef char CHAR8;
-typedef unsigned char UINT8;
+typedef uint8_t UINT8;
-typedef unsigned short UINT16;
+typedef uint16_t UINT16;
-typedef unsigned int UINT32;
+typedef uint32_t UINT32;
-typedef signed int INT32;
+typedef int32_t INT32;
-typedef unsigned long long UINT64;
+typedef uint64_t UINT64;
-typedef unsigned char BOOLEAN;
+typedef uint8_t BOOLEAN;
 
 #define DMSG_SB_TRACE   0x02
 #define TRACE(Arguments)

src/mainboard/amd/dinar/rd890_cfg.c

@@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
 	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+	pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry;
 
 	/*
 	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.

src/mainboard/amd/dinar/sb700_cfg.c

@@ -135,7 +135,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config)
 #ifndef __PRE_RAM__
 	/* ramstage cimx config here */
 	if (!sb_config->StdHeader.pCallBack) {
-		sb_config->StdHeader.pCallBack = sb700_callout_entry;
+		sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry;
 	}
 
 	//sb_config->

src/mainboard/supermicro/h8qgi/rd890_cfg.c

@@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
 	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+	pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry;
 
 	/*
 	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.

src/mainboard/supermicro/h8scm/rd890_cfg.c

@@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
 	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+	pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry;
 
 	/*
 	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.

src/mainboard/tyan/s8226/rd890_cfg.c

@@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON
 	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
 	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
 	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
-	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+	pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry;
 
 	/*
 	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.

src/northbridge/amd/cimx/rd890/amd.h

@@ -41,7 +41,7 @@
 #define OUT
 #define IMAGE_SIGNATURE 'DMA$'
 
-typedef UINTN AGESA_STATUS;
+typedef UINT32 AGESA_STATUS;
 
 
 #define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)

src/vendorcode/amd/agesa/common/Porting.h

@@ -216,6 +216,7 @@
 
 #elif defined __GNUC__
 
+  #include <stdint.h>
   #define IN
   #define OUT
   #define STATIC static
@@ -228,17 +229,20 @@
   #define CALLCONV
   #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
 
+
+    // Create the universal 32, 16, and 8-bit data types
   typedef unsigned char  BOOLEAN;
-  typedef   signed char  INT8;
+  typedef uintptr_t      UINTN;
-  typedef   signed short INT16;
+  typedef int64_t        INT64;
-  typedef   signed long  INT32;
+  typedef uint64_t       UINT64;
+  typedef int32_t        INT32;
+  typedef uint32_t       UINT32;
+  typedef int16_t        INT16;
+  typedef uint16_t       UINT16;
+  typedef int8_t         INT8;
+  typedef uint8_t        UINT8;
   typedef char         CHAR8;
-  typedef unsigned char  UINT8;
+  typedef unsigned short CHAR16;
-  typedef unsigned short UINT16;
-  typedef unsigned long  UINT32;
-  typedef unsigned long  UINTN;
-  typedef unsigned long  long UINT64;
-  typedef long  long INT64;
   typedef void VOID;
   //typedef unsigned long  size_t;
 

src/vendorcode/amd/cimx/sb700/SBTYPE.h

@@ -32,7 +32,7 @@
 
 #pragma pack(push,1)
 
-typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig);
+typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig);
 typedef void (*SMM_SERVICE_ROUTINE) (void);
 
 typedef struct _STDCFG{

src/vendorcode/amd/cimx/sb800/AMDSBLIB.h

@@ -46,6 +46,8 @@
 #ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
 #define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__
 
+#include <cpu/amd/common/cbtypes.h>
+
 //AMDSBLIB Routines
 
 /**
@@ -105,7 +107,7 @@ AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
  * @param[in] Length - Data length
  *
  */
-void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
+void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length);
 
 
 /* SB800 CIMx and AGESA V5 can share lib functions */

src/vendorcode/amd/cimx/sb900/AmdSbLib.h

@@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index);
 AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
 
 /**< AmdSbCopyMem - Reserved  */
-void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
+void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length);
 
 /**< GetRomSigPtr - Reserved  */
-void* GetRomSigPtr (IN unsigned int* RomSigPtr);
+void* GetRomSigPtr (IN UINTN * RomSigPtr);
 
 /**< RWXhciIndReg - Reserved  */
 void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);

src/vendorcode/amd/cimx/sb900/SbDef.h

@@ -71,7 +71,7 @@ void
 MemoryCopy (
   IN       unsigned char *Dest,
   IN       unsigned char *Source,
-  IN       unsigned int Size
+  IN       unsigned long Size
   );
 
 //AMD Library Routines (PCILIB.C)

src/vendorcode/amd/cimx/sb900/SbMain.c

@@ -278,7 +278,7 @@ sbSmmAcpiOn (
 UINTN
 CallBackToOEM (
   IN       UINT32 Func,
-  IN       UINT32 Data,
+  IN       UINTN  Data,
   IN       AMDSBCFG* pConfig
   )
 {

src/vendorcode/amd/cimx/sb900/SbSubFun.h

@@ -40,6 +40,7 @@
 ;
 ;*********************************************************************************/
 
+#include <cpu/amd/common/cbtypes.h>
 // Southbridge SBMAIN Routines
 
 /**
@@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
  * @param[in] Data    Callback specific data.
  * @param[in] pConfig Southbridge configuration structure pointer.
  */
-unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
+UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig);
 
 
 // Southbridge SBPOR Routines