drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal
This patch adds a driver for a new RTC from Micro Crystal. Supported features are: * configure backup voltage switchover via devicetree * configure backup capacitor charging mode via devicetree * set date if a voltage drop on backup voltage was detected to either a user definable (devicetree) or coreboot build date Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Werner Zeh
Felix Held
parent
2c789782ad
commit
5fb66adc32
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config DRIVERS_I2C_RV3028C7
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bool
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default n
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help
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Enable support for external RTC chip RV-3028-C7
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ramstage-$(CONFIG_DRIVERS_I2C_RV3028C7) += rv3028c7.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __DRIVERS_I2C_RV3028C7_CHIP_H__
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#define __DRIVERS_I2C_RV3028C7_CHIP_H__
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#include "rv3028c7.h"
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/*
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* The RTC has three different modes in how the backup voltage is used:
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* - OFF: Backup voltage not used
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* - DIRECT: Switch to backup voltage if it is higher than VDD
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* - LEVEL: Switch to backup voltage if VDD is < 2 V and VBACKUP > 2 V
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*/
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enum sw_mode {
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BACKUP_SW_DIRECT = 1,
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BACKUP_SW_OFF,
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BACKUP_SW_LEVEL
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};
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/*
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* The RTC can be used to charge a capacitor on VBACKUP.
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* There are the following modes:
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* - OFF: Do not charge the backup capacitor via VDD
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* - VIA_3K: Connect the backup capacitor via 3 k resistor with VDD
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* - VIA_5K: Connect the backup capacitor via 5 k resistor with VDD
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* - VIA_9K: Connect the backup capacitor via 9 k resistor with VDD
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* - VIA_15K: Connect the backup capacitor via 15 k resistor with VDD
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*/
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enum charge_mode {
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CHARGE_OFF = 0,
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CHARGE_VIA_3K,
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CHARGE_VIA_5K,
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CHARGE_VIA_9K,
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CHARGE_VIA_15K
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};
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struct drivers_i2c_rv3028c7_config {
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unsigned char user_weekday; /* User day of the week to set */
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unsigned char user_day; /* User day to set */
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unsigned char user_month; /* User month to set */
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unsigned char user_year; /* User year to set (2-digit) */
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unsigned char set_user_date; /* Use user date from devicetree */
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enum sw_mode bckup_sw_mode; /* Mode for switching between VDD and VBACKUP */
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enum charge_mode cap_charge; /* Mode for capacitor charging */
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};
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#endif /* __DRIVERS_I2C_RV3028C7_CHIP_H__ */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/bsd/bcd.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/i2c_bus.h>
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#include <timer.h>
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#include <types.h>
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#include <version.h>
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#include "chip.h"
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#include "rv3028c7.h"
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static enum cb_err rtc_eep_wait_ready(struct device *dev)
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{
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struct stopwatch sw;
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uint8_t status;
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stopwatch_init_msecs_expire(&sw, EEP_SYNC_TIMEOUT_MS);
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do {
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status = (uint8_t)i2c_dev_readb_at(dev, STATUS_REG);
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mdelay(1);
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} while ((status & EE_BUSY_BIT) && !stopwatch_expired(&sw));
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if (status & EE_BUSY_BIT) {
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return CB_ERR;
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} else {
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return CB_SUCCESS;
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}
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}
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static enum cb_err rtc_eep_auto_refresh(struct device *dev, uint8_t state)
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{
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uint8_t reg;
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reg = (uint8_t)i2c_dev_readb_at(dev, CTRL1_REG);
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reg &= ~EERD_BIT;
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if (state == EEP_REFRESH_DIS)
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reg |= EERD_BIT;
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i2c_dev_writeb_at(dev, CTRL1_REG, reg);
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/* Wait until the EEPROM has finished a possible running operation. */
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if (rtc_eep_wait_ready(dev) != CB_SUCCESS) {
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printk(BIOS_ERR, "%s: EEPROM access timed out (%d ms)!\n",
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dev->chip_ops->name, EEP_SYNC_TIMEOUT_MS);
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return CB_ERR;
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}
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return CB_SUCCESS;
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}
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static enum cb_err rtc_eep_start_update(struct device *dev)
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{
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/* Disable EEPROM auto refresh before writing RAM to EEPROM
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to avoid race conditions. */
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if (rtc_eep_auto_refresh(dev, EEP_REFRESH_DIS))
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return CB_ERR;
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/* Now start the update cycle.*/
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i2c_dev_writeb_at(dev, EEP_CMD_REG, EEP_CMD_PREFIX);
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i2c_dev_writeb_at(dev, EEP_CMD_REG, EEP_CMD_UPDATE);
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return CB_SUCCESS;
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}
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static void rtc_set_time_date(struct device *dev)
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{
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struct drivers_i2c_rv3028c7_config *config = dev->chip_info;
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uint8_t buf[7];
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/* The buffer contains the seconds through years of the new time and date.
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Whenever a new date is set, the time is set to 00:00:00. */
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buf[0] = 0; /* Entry for seconds. */
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buf[1] = 0; /* Entry for minutes. */
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buf[2] = 0; /* Entry for hours. */
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if (config->set_user_date) {
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buf[3] = config->user_weekday;
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buf[4] = bin2bcd(config->user_day);
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buf[5] = bin2bcd(config->user_month);
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buf[6] = bin2bcd(config->user_year);
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printk(BIOS_DEBUG, "%s: Set to user date\n", dev->chip_ops->name);
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} else {
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buf[3] = coreboot_build_date.weekday;
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buf[4] = coreboot_build_date.day;
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buf[5] = coreboot_build_date.month;
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buf[6] = coreboot_build_date.year;
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printk(BIOS_DEBUG, "%s: Set to coreboot build date\n", dev->chip_ops->name);
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}
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/* According to the datasheet, date and time should be transferred in "one go"
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in order to avoid value corruption. */
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if (i2c_dev_write_at(dev, buf, sizeof(buf), 0) != sizeof(buf)) {
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printk(BIOS_ERR, "%s: Not able to set date and time!\n", dev->chip_ops->name);
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}
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}
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static void rtc_final(struct device *dev)
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{
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uint8_t buf[7];
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/* Read back current RTC date and time and print it to the console.
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Date and time are read in "one go", the buffer contains seconds (byte 0)
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through years (byte 6) after this read. */
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if (i2c_dev_read_at(dev, buf, sizeof(buf), 0) != sizeof(buf)) {
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printk(BIOS_ERR, "%s: Not able to read current date and time!\n",
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dev->chip_ops->name);
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} else {
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printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n",
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dev->chip_ops->name, bcd2bin(buf[5]), bcd2bin(buf[4]),
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bcd2bin(buf[6]), bcd2bin(buf[2]), bcd2bin(buf[1]),
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bcd2bin(buf[0]));
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}
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/* Make sure the EEPROM automatic refresh is enabled. */
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if (rtc_eep_auto_refresh(dev, EEP_REFRESH_EN) != CB_SUCCESS) {
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printk(BIOS_ERR, "%s: Not able to enable EEPROM auto refresh!\n",
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dev->chip_ops->name);
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}
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}
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static void rtc_init(struct device *dev)
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{
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struct drivers_i2c_rv3028c7_config *config = dev->chip_info;
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uint8_t reg, backup_reg, eep_update_needed = 0;
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/* On every startup, the RTC synchronizes the internal EEPROM with RAM.
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* During this time no operation shall modify RAM registers. Ensure this
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* sync is finished before starting the initialization. */
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if (rtc_eep_wait_ready(dev) != CB_SUCCESS) {
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printk(BIOS_WARNING, "%s: Timeout on EEPROM sync after power on!\n",
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dev->chip_ops->name);
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return;
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}
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reg = backup_reg = (uint8_t)i2c_dev_readb_at(dev, EEP_BACKUP_REG);
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/* Configure the switch-over setting according to devicetree. */
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if (config->bckup_sw_mode) {
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reg &= ~BSM_MASK;
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reg |= config->bckup_sw_mode << BSM_BIT;
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}
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/* Configure the VBACKUP charging mode. */
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if (config->cap_charge) {
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reg &= ~TCR_MASK;
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reg |= ((config->cap_charge - 1) << TCR_BIT);
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reg |= TCE_BIT;
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} else {
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reg &= ~TCE_BIT;
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}
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/* According to the datasheet the Fast Edge Detection Enable (FEDE) bit
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should always be set. */
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reg |= FEDE_BIT;
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if (reg != backup_reg) {
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/* Write new register value into shadow RAM and request an EEPROM update. */
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i2c_dev_writeb_at(dev, EEP_BACKUP_REG, reg);
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eep_update_needed = 1;
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}
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/* Make sure the hour register is in 24h format.*/
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reg = (uint8_t)i2c_dev_readb_at(dev, CTRL2_REG);
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if (reg & HOUR_12_24_BIT) {
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reg &= ~HOUR_12_24_BIT;
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i2c_dev_writeb_at(dev, CTRL2_REG, reg);
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}
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/* Check for a possible voltage drop event. */
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reg = (uint8_t)i2c_dev_readb_at(dev, STATUS_REG);
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if (reg & PORF_BIT) {
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/* Voltage drop was detected, date and time needs to be set properly. */
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rtc_set_time_date(dev);
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/* Clear the PORF bit to mark that the event was handled. */
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reg &= ~PORF_BIT;
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i2c_dev_writeb_at(dev, STATUS_REG, reg);
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}
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/*
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* Finally, trigger the EEPROM update procedure if needed.
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* According to the datasheet, this update will consume ~63 ms.
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* In order to not block the boot process here waiting for this update being finished,
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* trigger the update now and check for readiness in the final hook.
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*/
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if (eep_update_needed && rtc_eep_start_update(dev) != CB_SUCCESS) {
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printk(BIOS_ERR, "%s: Not able to trigger EEPROM update!\n",
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dev->chip_ops->name);
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}
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}
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static struct device_operations rv3028c7_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = rtc_init,
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.final = rtc_final,
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};
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static void rtc_enable(struct device *dev)
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{
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dev->ops = &rv3028c7_ops;
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}
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struct chip_operations drivers_i2c_rv3028c7_ops = {
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CHIP_NAME("RV-3028-C7")
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.enable_dev = rtc_enable
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};
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _I2C_RV3028C7_H_
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#define _I2C_RV3028C7_H_
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/* Register layout */
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#define SECOND_REG 0x00
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#define MINUTE_REG 0x01
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#define HOUR_REG 0x02
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#define WEEK_REG 0x03
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#define DAY_REG 0x04
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#define MONTH_REG 0x05
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#define YEAR_REG 0x06
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#define STATUS_REG 0x0e
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#define PORF_BIT (1 << 0)
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#define EE_BUSY_BIT (1 << 7)
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#define CTRL1_REG 0x0f
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#define EERD_BIT (1 << 3)
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#define CTRL2_REG 0x10
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#define HOUR_12_24_BIT (1 << 1)
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/* Registers for the internal EEPROM */
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#define EEP_ADR_REG 0x25
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#define EEP_DATA_REG 0x26
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#define EEP_CMD_REG 0x27
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#define EEP_CMD_PREFIX 0x00
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#define EEP_CMD_UPDATE 0x11
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#define EEP_BACKUP_REG 0x37
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#define FEDE_BIT (1 << 4)
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#define BSM_BIT 2
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#define BSM_MASK (3 << BSM_BIT)
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#define TCR_BIT 0
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#define TCR_MASK (3 << TCR_BIT)
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#define TCE_BIT (1 << 5)
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#define EEP_REFRESH_EN 1
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#define EEP_REFRESH_DIS 0
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/* The longest mentioned timeout in the datasheet is 63 ms,
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round up to 70 ms to be on the safe side. */
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#define EEP_SYNC_TIMEOUT_MS 70
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#endif /* _I2C_RV3028C7_H_ */
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