From 5fc0afbc170960d05012eec9b3b8717f65a07478 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 14 Apr 2023 01:06:22 +0300 Subject: [PATCH] asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FADT duty_width/duty_offset fields, together with P_CNT (previously P_BLK) IO address are provided with _PTC entry. FADT p_lvl2/3_lat fields had values that disabled C2/C3 state transitions so _CST entries are not required. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82371eb/acpi_tables.c | 8 +++++--- src/southbridge/intel/i82371eb/fadt.c | 3 --- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index a4cd1b3102..a9b9949fdf 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -8,10 +8,12 @@ static void generate_cpu_entry(int cpu) { - int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6; + acpigen_write_processor_device(cpu); - acpigen_write_processor(cpu, pcontrol_blk, plen); - acpigen_pop_len(); + /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ + acpigen_write_PTC(3, 1, DEFAULT_PMBASE + PCNTRL); + + acpigen_write_processor_device_end(); } void generate_cpu_entries(const struct device *device) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 43e119b746..551ec8fbde 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -29,9 +29,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ - fadt->duty_width = 3; /* this width is in bits */ - /* * bit meaning * 0 1: We have user-visible legacy devices