get include files right
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Greg Watson
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/*kernel/include/sys/as_archppc970.h, epos_code, epos_1.0 8/25/04 15:33:07*/
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/*----------------------------------------------------------------------------+
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| COPYRIGHT I B M CORPORATION 2003
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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| US Government Users Restricted Rights - Use, duplication or
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| disclosure restricted by GSA ADP Schedule Contract with
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| IBM Corp.
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| EPOS
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| Author: Maciej P. Tyrlik
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| Component: Include file.
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| File: sys/as_archppc970.h
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| Purpose: Assembler include file for PPC970 processor.
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| Changes:
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| Date: Comment:
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| ----- --------
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| 13-Oct-03 Created MPT
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+----------------------------------------------------------------------------*/
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#ifndef _sys_as_archppc970_h_
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#define _sys_as_archppc970_h_
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/*----------------------------------------------------------------------------+
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| PVR value.
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+----------------------------------------------------------------------------*/
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#define PVR_970_DD1 0x00391100
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#define PVR_970FX_DD2 0x003C0200
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#define PVR_970FX_DD2_1 0x003C0201
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#define PVR_970FX_DD3 0x003C0300
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/*----------------------------------------------------------------------------+
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| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)
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| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32)
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| registers are defined in as_archppc.h.
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+----------------------------------------------------------------------------*/
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#define SPR_ACCR 0x001D /* 64-bit read/write $*/
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#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */
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#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */
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#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */
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#define SPR_DAR 0x0013 /* 64-bit read/write */
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#define SPR_DEC 0x0016 /* 32-bit read/write */
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#define SPR_DSISR 0x0012 /* 32-bit read/write */
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#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */
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#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */
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#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */
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#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */
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#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */
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#define SPR_HIOR 0x0137 /* 64-bit read/write */
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#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */
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#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */
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#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */
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#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */
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#define SPR_IMC 0x030F /* 64-bit read/write */
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#define SPR_MMCR0 0x031B /* 64-bit read/write */
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#define SPR_MMCR1 0x031E /* 64-bit read/write */
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#define SPR_MMCRA 0x0312 /* 64-bit read/write */
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#define SPR_PIR 0x03FF /* 32-bit read */
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#define SPR_PMC1 0x0313 /* 32-bit read/write */
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#define SPR_PMC2 0x0314 /* 32-bit read/write */
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#define SPR_PMC3 0x0315 /* 32-bit read/write */
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#define SPR_PMC4 0x0316 /* 32-bit read/write */
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#define SPR_PMC5 0x0317 /* 32-bit read/write */
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#define SPR_PMC6 0x0318 /* 32-bit read/write */
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#define SPR_PMC7 0x0319 /* 32-bit read/write */
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#define SPR_PMC8 0x031A /* 32-bit read/write */
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#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */
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#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */
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#define SPR_SDAR 0x031D /* 64-bit read/write */
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#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */
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#define SPR_SIAR 0x031C /* 64-bit read/write */
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#define SPR_TBL_WRITE 0x011C /* 32-bit write */
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#define SPR_TBU_WRITE 0x011D /* 32-bit write */
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#define SPR_TRACE 0x03FE /* 64-bit read $*/
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#define SPR_TRIG0 0x03D0 /* 64-bit write */
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#define SPR_TRIG1 0x03D1 /* 64-bit write */
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#define SPR_TRIG2 0x03D2 /* 64-bit write */
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#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/
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/*----------------------------------------------------------------------------+
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| Vector status and control register is accessed using the mfvscr and mtvscr
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| instructions.
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
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| register bits are defined in as_archppc.h. This is a 64-bit register.
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+----------------------------------------------------------------------------*/
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#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */
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#define MSR_HV 0x1000000000000000 /* hypervisor mode */
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#define MSR_VMX 0x0000000002000000 /* vmx unit available */
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#define MSR_POW 0x0000000000040000 /* power management enable */
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#define MSR_SE 0x0000000000000400 /* single step */
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#define MSR_BE 0x0000000000000200 /* branch trace */
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#define MSR_IS 0x0000000000000020 /* instruction address space */
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#define MSR_DS 0x0000000000000010 /* data address space */
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#define MSR_PM 0x0000000000000004 /* performance monitor */
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#define MSR_RI 0x0000000000000002 /* recoverable interrupt */
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/*----------------------------------------------------------------------------+
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| HID0 bits.
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+----------------------------------------------------------------------------*/
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#define HID0_ONEPPC 0x8000000000000000
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#define HID0_SINGLE 0x4000000000000000
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#define HID0_ISYNC_SC 0x2000000000000000
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#define HID0_SERIAL_G 0x1000000000000000
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#define HID0_DEEP_NAP 0x0100000000000000
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#define HID0_NAP 0x0040000000000000
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#define HID0_DPM 0x0010000000000000
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#define HID0_TR_GR 0x0004000000000000
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#define HID0_TR_DIS 0x0002000000000000
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#define HID0_NHR 0x0001000000000000
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#define HID0_INORDER 0x0000800000000000
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#define HID0_ENH_TR 0x0000400000000000
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#define HID0_TB_CTRL 0x0000200000000000
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#define HID0_EXT_TB_EN 0x0000100000000000
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#define HID0_CIABR_EN 0x0000020000000000
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#define HID0_HDEC_EN 0x0000010000000000
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#define HID0_EB_THERM 0x0000008000000000
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#define HID0_EN_ATTN 0x0000000100000000
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#define HID0_EN_MAC 0x0000000080000000
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/*----------------------------------------------------------------------------+
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| HID1 bits.
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+----------------------------------------------------------------------------*/
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#define HID1_BHT_PM 0xE000000000000000
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#define HID1_BHT_STATIC 0x0000000000000000
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#define HID1_BHT_GLOBAL 0x4000000000000000
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#define HID1_BHT_LOCAL 0x8000000000000000
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#define HID1_BHT_GL_LO 0xC000000000000000
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#define HID1_BHT_GL_CO 0x6000000000000000
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#define HID1_BHT_FULL 0xE000000000000000
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#define HID1_EN_LS 0x1000000000000000
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#define HID1_EN_CC 0x0800000000000000
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#define HID1_EN_IC 0x0400000000000000
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#define HID1_PF_MASK 0x0180000000000000
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#define HID1_PF_NSA 0x0080000000000000
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#define HID1_PF_NSA_P 0x0100000000000000
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#define HID1_PF_DIS 0x0180000000000000
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#define HID1_EN_ICBI 0x0040000000000000
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#define HID1_EN_IF_CACH 0x0020000000000000
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#define HID1_EN_IC_REC 0x0010000000000000
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#define HID1_EN_ID_REC 0x0008000000000000
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#define HID1_EN_ER_REC 0x0004000000000000
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#define HID1_IC_PE 0x0002000000000000
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#define HID1_ICD0_PE 0x0001000000000000
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#define HID1_ICD1_PE 0x0000800000000000
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#define HID1_IER_PE 0x0000400000000000
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#define HID1_EN_SP_ITW 0x0000200000000000
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#define HID1_S_CHICKEN 0x0000100000000000
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/*----------------------------------------------------------------------------+
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| HID4 bits.
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+----------------------------------------------------------------------------*/
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#define HID4_LPES0 0x8000000000000000
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#define HID4_RMLR12_MSK 0x6000000000000000
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#define HID4_LPID25_MSK 0x1E00000000000000
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#define HID4_RMOR_MASK 0x01FFFE0000000000
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#define HID4_RM_CI 0x0000010000000000
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#define HID4_FORCE_AI 0x0000008000000000
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#define HID4_DIS_PERF 0x0000004000000000
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#define HID4_RES_PERF 0x0000002000000000
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#define HID4_EN_SP_DTW 0x0000001000000000
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#define HID4_L1DC_FLSH 0x0000000800000000
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#define HID4_D_DERAT_P1 0x0000000400000000
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#define HID4_D_DERAT_P2 0x0000000200000000
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#define HID4_D_DERAT_G 0x0000000100000000
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#define HID4_D_DERAT_S1 0x0000000040000000
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#define HID4_D_DERAT_S2 0x0000000080000000
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#define HID4_DC_TP_S1 0x0000000020000000
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#define HID4_DC_TP_S2 0x0000000010000000
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#define HID4_DC_TP_GEN 0x0000000008000000
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#define HID4_DC_SET1 0x0000000004000000
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#define HID4_DC_SET2 0x0000000002000000
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#define HID4_DC_DP_S1 0x0000000001000000
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#define HID4_DC_DP_S2 0x0000000000800000
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#define HID4_DC_DP_GEN 0x0000000000400000
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#define HID4_R_TAG1P_CH 0x0000000000200000
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#define HID4_R_TAG2P_CH 0x0000000000100000
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#define HID4_TLB_PC1 0x0000000000080000
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#define HID4_TLB_PC2 0x0000000000040000
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#define HID4_TLB_PC3 0x0000000000020000
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#define HID4_TLB_PC4 0x0000000000010000
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#define HID4_TLB_P_GEN 0x0000000000008000
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#define HID4_TLB_SET1 0x0000000000003800
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#define HID4_TLB_SET2 0x0000000000005800
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#define HID4_TLB_SET3 0x0000000000006800
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#define HID4_TLB_SET4 0x0000000000007000
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#define HID4_DIS_SLBPC 0x0000000000000400
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#define HID4_DIS_SLBPG 0x0000000000000200
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#define HID4_MCK_INJ 0x0000000000000100
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#define HID4_DIS_STFWD 0x0000000000000080
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#define HID4_LPES1 0x0000000000000040
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#define HID4_RMLR0_MSK 0x0000000000000020
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#define HID4_DIS_SPLARX 0x0000000000000008
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#define HID4_LP_PG_EN 0x0000000000000004
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#define HID4_LPID01_MSK 0x0000000000000003
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/*----------------------------------------------------------------------------+
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| HID5 bits.
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+----------------------------------------------------------------------------*/
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#define HID5_HRMOR_MASK 0x00000000FFFF0000
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#define HID5_DC_MCK 0x0000000000002000
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#define HID5_DIS_PWRSAV 0x0000000000001000
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#define HID5_FORCE_G 0x0000000000000800
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#define HID5_DC_REPL 0x0000000000000400
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#define HID5_HWR_STMS 0x0000000000000200
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#define HID5_DST_NOOP 0x0000000000000100
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#define HID5_DCBZ_SIZE 0x0000000000000080
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#define HID5_DCBZ32_ILL 0x0000000000000040
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#define HID5_TLB_MAP 0x0000000000000020
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#define HID5_IMQ_PORT 0x0000000000000010
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#define HID5_LMP_SIZE0 0x0000000000000008
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#define HID5_DPFLOOD 0x0000000000000004
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#define HID5_TCH_NOP 0x0000000000000002
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#define HID5_LMP_SIZE1 0x0000000000000001
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/*----------------------------------------------------------------------------+
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| Specific SRR1 bit definitions for Machine Check.
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+----------------------------------------------------------------------------*/
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#define SRR1_IFU_UNREC 0x0000000000200000
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#define SRR1_LOAD_STORE 0x0000000000100000
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#define SRR1_SLB_PARITY 0x0000000000040000
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#define SRR1_TLB_PARITY 0x0000000000080000
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#define SRR1_ITLB_RELOA 0x00000000000C0000
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#define SRR1_RI 0x0000000000000002
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#endif /* _sys_as_archppc970_h_ */
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@ -3,17 +3,13 @@
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##
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uses _RAMBASE
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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##
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## Use cache ram for initial setup
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## Assumes RAM already initialiazed
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## This is true for the Apache board, but may
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## not be for other 970 systems.
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##
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default USE_DCACHE_RAM=1
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## Set dcache ram above linuxbios image
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default DCACHE_RAM_BASE=_RAMBASE+0x100000
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## Dcache size is 32Kb
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default DCACHE_RAM_SIZE=0x8000
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default USE_DCACHE_RAM=0
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initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc
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@ -29,9 +29,7 @@
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| 10-Feb-04 Port to PPC970FX MPT
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+----------------------------------------------------------------------------*/
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#include <sys/as_archppc.h>
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#include <sys/as_archppc970.h>
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#include <ppc970fx_board.h>
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#include <ppc970.h>
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/*----------------------------------------------------------------------------+
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| Local defines.
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@ -44,7 +42,6 @@
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| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.
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| Data cahability must be turned on. Instruction cahability must be off.
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+----------------------------------------------------------------------------*/
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function_prolog(init_core)
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/*--------------------------------------------------------------------+
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| Set time base to 0.
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+--------------------------------------------------------------------*/
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@ -366,4 +363,3 @@ function_prolog(init_core)
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eieio
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mtspr SPR_SRR0,r0
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rfid
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function_epilog(init_core)
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