mb/google/volteer: Update TCSS D3Hot and D3Cold configuration
It is expected TCSS D3Hot is enabled. D3Cold configuration is through SoC stepping determination. D3Cold is disabled on pre-QS platform and enabled on QS platform. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -170,10 +170,6 @@ chip soc/intel/tigerlake
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register "IomTypeCPortPadCfg[6]" = "0x09000000"
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register "IomTypeCPortPadCfg[7]" = "0x09000000"
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# D3Hot and D3Cold for TCSS
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register "TcssD3HotEnable" = "1"
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register "TcssD3ColdEnable" = "0"
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# DP port
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register "DdiPortAConfig" = "1" # eDP
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register "DdiPortBConfig" = "0"
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