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mb/google/volteer: Update TCSS D3Hot and D3Cold configuration 

It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.

BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2020-07-28 12:51:53 -07:00 committed by Nick Vaccaro
parent bd615d6f93
commit 5fdf2760a5
1 changed files with 0 additions and 4 deletions
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4
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -170,10 +170,6 @@ chip soc/intel/tigerlake
register "IomTypeCPortPadCfg[6]" = "0x09000000" register "IomTypeCPortPadCfg[6]" = "0x09000000"
register "IomTypeCPortPadCfg[7]" = "0x09000000" register "IomTypeCPortPadCfg[7]" = "0x09000000"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "0"
# DP port # DP port
register "DdiPortAConfig" = "1" # eDP register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0" register "DdiPortBConfig" = "0"