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cpu/amd (non-AGESA): Load microcode updates from CBFS 

Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4502
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
Kyösti Mälkki 2013-12-08 07:21:05 +02:00 committed by Alexandru Gagniuc
parent 893b81f79f
commit 5fe1fb7a5f
11 changed files with 85 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
src/cpu/amd/microcode/microcode.c
View File

@ -21,6 +21,10 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
struct microcode {
u32 date_code;
@ -51,40 +55,60 @@ struct microcode {
u8 x86_code_entry[191];
};
void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_id)
static void apply_microcode_patch(const struct microcode *m)
{
u32 patch_id, new_patch_id;
struct microcode *m;
char *c;
uint32_t new_patch_id;
msr_t msr;
/* apply patch */
msr.hi = 0;
msr.lo = (uint32_t)m;
wrmsr(0xc0010020, msr);
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
/* read the patch_id again */
msr = rdmsr(0x8b);
patch_id = msr.lo;
new_patch_id = msr.lo;
printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
(new_patch_id == m->patch_id) ? "success" : "fail");
}
m = microcode_updates;
for(c = microcode_updates; m->date_code; m = (struct microcode *)c) {
static void amd_update_microcode(const void *ucode, size_t ucode_len,
uint32_t equivalent_processor_rev_id)
{
const struct microcode *m;
const void *c;
for(m = c = ucode; m->date_code; m = c) {
if (m->processor_rev_id == equivalent_processor_rev_id) {
//apply patch
msr.hi = 0;
msr.lo = (u32)m;
wrmsr(0xc0010020, msr);
printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
//read the patch_id again
msr = rdmsr(0x8b);
new_patch_id = msr.lo;
printk(BIOS_DEBUG, "microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
apply_microcode_patch(m);
break;
}
c += 2048;
}
}
#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id)
{
const void *ucode;
size_t ucode_len;
if (equivalent_processor_rev_id == 0) {
UCODE_DEBUG("rev id not found. Skipping microcode patch!\n");
return;
}
ucode = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, MICROCODE_CBFS_FILE,
CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
return;
}
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
}

1
src/cpu/amd/model_10xxx/Kconfig
View File

@ -9,6 +9,7 @@ config CPU_AMD_MODEL_10XXX
select MMCONF_SUPPORT_DEFAULT
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
if CPU_AMD_MODEL_10XXX

2
src/cpu/amd/model_10xxx/Makefile.inc
View File

@ -4,3 +4,5 @@ ramstage-y += processor_name.c
romstage-y += update_microcode.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c

9
src/cpu/amd/model_10xxx/microcode_blob.c Normal file
View File

@ -0,0 +1,9 @@
unsigned char microcode[] __attribute__ ((aligned(16))) = {
#include CONFIG_AMD_UCODE_PATCH_FILE
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};

27
src/cpu/amd/model_10xxx/update_microcode.c
View File

@ -19,13 +19,8 @@
*/
#include <stdint.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
#ifdef __PRE_RAM__
/* From the Revision Guide :
* Equivalent Processor Table for AMD Family 10h Processors
*
@ -47,16 +42,6 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
* 00100FA0h (PH-E0) 10A0h 010000bfh
*/
#include CONFIG_AMD_UCODE_PATCH_FILE
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};
struct id_mapping {
uint32_t orig_id;
uint16_t new_id;
@ -101,14 +86,6 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) {
void update_microcode(u32 cpu_deviceid)
{
u32 equivalent_processor_rev_id;
/* Update the microcode */
equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
if (equivalent_processor_rev_id != 0) {
amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
} else {
printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n");
}
u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
}

1
src/cpu/amd/model_fxx/Kconfig
View File

@ -9,6 +9,7 @@ config CPU_AMD_MODEL_FXX
select SSE2
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
if CPU_AMD_MODEL_FXX
config UDELAY_IO

2
src/cpu/amd/model_fxx/Makefile.inc
View File

@ -5,3 +5,5 @@ ramstage-y += model_fxx_init.c
ramstage-y += model_fxx_update_microcode.c
ramstage-y += processor_name.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c

13
src/cpu/amd/model_fxx/microcode_blob.c Normal file
View File

@ -0,0 +1,13 @@
unsigned char microcode[] __attribute__ ((aligned(16))) = {
#if !CONFIG_K8_REV_F_SUPPORT
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};

2
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -468,7 +468,7 @@ static void model_fxx_init(device_t dev)
x86_mtrr_check();
/* Update the microcode */
model_fxx_update_microcode(dev->device);
update_microcode(dev->device);
disable_cache();

27
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@ -23,24 +23,6 @@
#include <console/console.h>
#include <cpu/amd/microcode.h>
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
#if !CONFIG_K8_REV_F_SUPPORT
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
#if CONFIG_K8_REV_F_SUPPORT
// #include "microcode_rev_f.h"
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};
struct id_mapping {
uint32_t orig_id;
uint16_t new_id;
@ -95,12 +77,11 @@ static u16 get_equivalent_processor_rev_id(u32 orig_id) {
return new_id;
}
void model_fxx_update_microcode(unsigned cpu_deviceid)
void update_microcode(uint32_t cpu_deviceid)
{
unsigned equivalent_processor_rev_id;
uint32_t equivalent_rev_id;
/* Update the microcode */
equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
if(equivalent_processor_rev_id != 0)
amd_update_microcode(microcode_updates, equivalent_processor_rev_id);
equivalent_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
amd_update_microcode_from_cbfs(equivalent_rev_id);
}

5
src/include/cpu/amd/microcode.h
View File

@ -1,9 +1,8 @@
#ifndef CPU_AMD_MICROCODE_H
#define CPU_AMD_MICROCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
void model_fxx_update_microcode(unsigned cpu_deviceid);
void update_microcode(u32 processor_rev_id);
void update_microcode(u32 cpu_deviceid);
void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id);
#endif /* CPU_AMD_MICROCODE_H */