google/rambi: disable TXE in devicetree for all variants
The TXE PCI device serves no function under Linux, and doesn't work properly under Windows, so disable/hide it from the OS. Test: Boot Windows 10 on google/squawks, verify TXE not visible under Device Manager. Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
a86bbea04d
commit
5ff460fc2e
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 off end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 off end # PCIE_PORT2
|
||||
|
|
|
@ -62,7 +62,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 off end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -71,7 +71,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 off end # PCIE_PORT2
|
||||
|
|
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -71,7 +71,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -71,7 +71,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 on end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 off end # PCIE_PORT2
|
||||
|
|
|
@ -74,7 +74,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
|
@ -75,7 +75,7 @@ chip soc/intel/baytrail
|
|||
device pci 18.5 off end # I2C5
|
||||
device pci 18.6 off end # I2C6
|
||||
device pci 18.7 off end # I2C7
|
||||
device pci 1a.0 on end # TXE
|
||||
device pci 1a.0 off end # TXE
|
||||
device pci 1b.0 on end # HDA
|
||||
device pci 1c.0 on end # PCIE_PORT1
|
||||
device pci 1c.1 on end # PCIE_PORT2
|
||||
|
|
Loading…
Reference in New Issue