mb/google/brask/variants/moli: set up gpio
Set the GPIO configuration of moli BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
This commit is contained in:
Raihow Shi
Felix Held
parent
28a30426fe
commit
5ff5225962
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@ -0,0 +1,5 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,150 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A15 : USB_OC2# ==> DDIC_DP_HPD4 */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2),
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/* A21 : DDPC_CTRCLK ==> DDIC_DP_CTRCLK */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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/* A22 : DDPC_CTRLDATA ==> DDIC_DP_CTRLDATA */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : PROC_GP2 ==> EMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* C3 : SML0CLK ==> PCH_SML0_CLK */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* C4 : SML0DATA ==> PCH_SML0_DATA */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC(GPP_D9, NONE),
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/* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
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PAD_CFG_GPO(GPP_D14, 1, DEEP),
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/* D16 : ISH_UART0_CTS# ==> USB_A2_RT_RST_ODL */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* E1 : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */
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PAD_CFG_GPI(GPP_E1, NONE, DEEP),
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/* E2 : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E5, 1, DEEP),
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/* E12 : THC0_SPI1_IO1 ==> B2B_USBCCARD_DETN */
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PAD_NC(GPP_E12, NONE),
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/* E13 : THC0_SPI1_IO2 ==> B2B_SERIAL_DETN */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
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PAD_CFG_GPO(GPP_E20, 1, DEEP),
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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/* R4 : HDA_RST# ==> NC */
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PAD_NC(GPP_R4, NONE),
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/* R5 : HDA_SDI1 ==> NC */
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PAD_NC(GPP_R5, NONE),
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/* R6 : I2S2_TXD ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S2_RXD ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* GPD11: LANPHYC ==> LAN_DISABLE_N */
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PAD_CFG_GPO(GPD11, 0, DEEP),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D18 : UART1_TXD ==> SD_PE_RST_L */
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PAD_CFG_GPO(GPP_D18, 0, PLTRST),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* D18 : UART1_TXD ==> SD_PE_RST_L */
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PAD_CFG_GPO(GPP_D18, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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