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soc/intel/cannonlake: Add cannonlake ACPI GPIO op 

Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.

BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-12-27 17:01:09 -08:00 committed by Patrick Georgi
parent 334be3289d
commit 5ff742c740
6 changed files with 117 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
src/soc/intel/cannonlake/acpi.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -248,3 +248,40 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

20
src/soc/intel/cannonlake/acpi/gpio.asl
View File

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -16,7 +16,7 @@
#include <soc/gpio_defs.h>
#include <soc/irq.h>
#include <soc/pcr_ids.h>
#include "gpio_op.asl"
Device (GPIO)
{
@ -107,19 +107,3 @@ Method (GADD, 1, NotSerialized)
Add (Local2, PAD_CFG_BASE, Local2)
Return (Add (Local2, Multiply (Local1, 16)))
}
/*
* Get GPIO Value
* Arg0 - GPIO Number
*/
Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
Return (Local0)
}

18
src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
View File

@ -15,7 +15,7 @@
#include <soc/gpio_defs_cnp_h.h>
#include <soc/irq.h>
#include <soc/pcr_ids.h>
#include "gpio_op.asl"
Device (GPIO)
{
@ -107,19 +107,3 @@ Method (GADD, 1, NotSerialized)
Add (Local2, PAD_CFG_BASE, Local2)
Return (Add (Local2, Multiply (Local1, 16)))
}
/*
* Get GPIO Value
* Arg0 - GPIO Number
*/
Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
Return (Local0)
}

74
src/soc/intel/cannonlake/acpi/gpio_op.asl Normal file
View File

@ -0,0 +1,74 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Get GPIO Value
* Arg0 - GPIO Number
*/
Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
Return (Local0)
}
/*
* Get GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (GTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (GPIOTXSTATE_MASK, VAL0, Local0)
Return (Local0)
}
/*
* Set GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (STXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
Or (GPIOTXSTATE_MASK, VAL0, VAL0)
}
/*
* Clear GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (CTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (Not (GPIOTXSTATE_MASK), VAL0, VAL0)
}

1
src/soc/intel/cannonlake/include/soc/gpio_defs.h
View File

@ -252,4 +252,5 @@
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#define GPIOTXSTATE_MASK 0x1
#endif

1
src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
View File

@ -326,4 +326,5 @@
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#define GPIOTXSTATE_MASK 0x1
#endif