add Option.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
6a61d6a4ae
commit
6014983bab
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@ -0,0 +1,210 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses CC
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uses HOSTCC
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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###
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### Build options
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###
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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##
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default ROM_SIZE=524288
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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default FALLBACK_SIZE=131072
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Funky hard reset implementation
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##
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=2
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default HARD_RESET_FUNCTION=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=1
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="Tyan"
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default MAINBOARD_VENDOR="s2850"
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## LinuxBIOS C code runs at this location in RAM
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##
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_STREAM = 1
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###
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### Defaults of options that you may want to override in the target config file
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###
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##
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## The default compiler
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##
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default CC="gcc"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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##
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## Select power on after power fail setting
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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### End Options.lb
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end
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@ -111,7 +111,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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//#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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@ -0,0 +1,210 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses CC
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uses HOSTCC
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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||||
|
||||
|
||||
###
|
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### Build options
|
||||
###
|
||||
|
||||
##
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## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
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default ROM_SIZE=524288
|
||||
|
||||
##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
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default FALLBACK_SIZE=131072
|
||||
|
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##
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## Build code for the fallback boot
|
||||
##
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default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
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||||
default HAVE_HARD_RESET=1
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||||
|
||||
##
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## Funky hard reset implementation
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||||
##
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=5
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default HARD_RESET_FUNCTION=0
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##
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||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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||||
|
||||
##
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||||
## Build code for SMP support
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||||
## Only worry about 2 micro processors
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||||
##
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||||
default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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||||
##
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||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
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||||
default MAINBOARD_PART_NUMBER="Tyan"
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default MAINBOARD_VENDOR="s2875"
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||||
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||||
###
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||||
### LinuxBIOS layout values
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||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
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default STACK_SIZE=0x2000
|
||||
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##
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## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
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default _RAMBASE=0x00004000
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||||
|
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_STREAM = 1
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||||
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||||
###
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### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
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## The default compiler
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||||
##
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||||
default CC="gcc"
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default HOSTCC="gcc"
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##
|
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## The Serial Console
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##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
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#default TTYS0_BAUD=2400
|
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#default TTYS0_BAUD=1200
|
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|
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# Select the serial console base port
|
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default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
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## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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### End Options.lb
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||||
end
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||||
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@ -128,7 +128,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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}
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||||
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||||
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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//#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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||||
|
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@ -0,0 +1,210 @@
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|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
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||||
uses XIP_ROM_BASE
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uses STACK_SIZE
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||||
uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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||||
uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
|
||||
uses CC
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||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s2881"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s2881"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -123,7 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s2882"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -126,12 +126,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=3
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s2885"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -133,7 +133,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s4880"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -147,7 +147,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,210 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses USE_OPTION_TABLE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default FALLBACK_SIZE=131072
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Funky hard reset implementation
|
||||
##
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=4
|
||||
default HARD_RESET_FUNCTION=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default MAINBOARD_PART_NUMBER="Tyan"
|
||||
default MAINBOARD_VENDOR="s4882"
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
##
|
||||
default _RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="gcc"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -147,7 +147,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
//#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
|
|
|
|||
Loading…
Reference in New Issue