From 601a971545e30057dda17e77de854a0bd1f5f226 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 8 Dec 2021 16:13:01 +0100 Subject: [PATCH] soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/spi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 5c3bd0eac7..4efed68c49 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -71,8 +71,8 @@ enum spi100_speed { #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc7 -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) +#define SPI_FIFO_LAST_BYTE 0xc6 +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) struct spi_config { /*