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src: Replace MSR addresses with macros 

Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Elyes HAOUAS 2018-09-28 09:06:43 +02:00 committed by Martin Roth
parent de5d04011c
commit 603963e1ba
4 changed files with 11 additions and 11 deletions
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10
src/cpu/intel/microcode/microcode.c
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@ -102,7 +102,7 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
msr.lo = (unsigned long)m + sizeof(struct microcode); msr.lo = (unsigned long)m + sizeof(struct microcode);
msr.hi = 0; msr.hi = 0;
wrmsr(0x79, msr); wrmsr(IA32_BIOS_UPDT_TRIG, msr);
#if !defined(__ROMCC__) #if !defined(__ROMCC__)
printk(BIOS_DEBUG, "microcode: updated to revision " printk(BIOS_DEBUG, "microcode: updated to revision "
@ -158,12 +158,12 @@ const void *intel_microcode_find(void)
return NULL; return NULL;
#endif #endif
/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ /* CPUID sets MSR 0x8B if a microcode update has been loaded. */
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
wrmsr(0x8B, msr); wrmsr(IA32_BIOS_SIGN_ID, msr);
eax = cpuid_eax(1); eax = cpuid_eax(1);
msr = rdmsr(0x8B); msr = rdmsr(IA32_BIOS_SIGN_ID);
rev = msr.hi; rev = msr.hi;
x86_model = (eax >> 4) & 0x0f; x86_model = (eax >> 4) & 0x0f;
x86_family = (eax >> 8) & 0x0f; x86_family = (eax >> 8) & 0x0f;
@ -171,7 +171,7 @@ const void *intel_microcode_find(void)
pf = 0; pf = 0;
if ((x86_model >= 5) || (x86_family > 6)) { if ((x86_model >= 5) || (x86_family > 6)) {
msr = rdmsr(0x17); msr = rdmsr(IA32_PLATFORM_ID);
pf = 1 << ((msr.hi >> 18) & 7); pf = 1 << ((msr.hi >> 18) & 7);
} }
#if !defined(__ROMCC__) #if !defined(__ROMCC__)

4
src/northbridge/intel/haswell/report_platform.c
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@ -50,9 +50,9 @@ static void report_cpu_info(void)
microcode_ver.lo = 0; microcode_ver.lo = 0;
microcode_ver.hi = 0; microcode_ver.hi = 0;
wrmsr(0x8B, microcode_ver); wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1); cpuidr = cpuid(1);
microcode_ver = rdmsr(0x8b); microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name); printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;

4
src/soc/intel/broadwell/romstage/report_platform.c
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@ -113,9 +113,9 @@ static void report_cpu_info(void)
microcode_ver.lo = 0; microcode_ver.lo = 0;
microcode_ver.hi = 0; microcode_ver.hi = 0;
wrmsr(0x8B, microcode_ver); wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1); cpuidr = cpuid(1);
microcode_ver = rdmsr(0x8b); microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */ /* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {

4
src/soc/intel/skylake/bootblock/report_platform.c
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@ -145,9 +145,9 @@ static void report_cpu_info(void)
microcode_ver.lo = 0; microcode_ver.lo = 0;
microcode_ver.hi = 0; microcode_ver.hi = 0;
wrmsr(0x8B, microcode_ver); wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1); cpuidr = cpuid(1);
microcode_ver = rdmsr(0x8b); microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */ /* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {