haswell: cbmem_get_table_location() implementation
Provide the implemenation of cbmem_get_table_location() so that cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT is enabled. The cbmem tables are located just below the TSEG region. Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2798 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -418,10 +418,6 @@ static void mc_add_dram_resources(device_t dev)
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mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
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CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
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#endif
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/* Leave some space for ACPI, PIRQ and MP tables */
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high_tables_size = HIGH_MEMORY_SIZE;
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high_tables_base = mc_values[TSEG_REG] - high_tables_size;
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}
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static void mc_read_resources(device_t dev)
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@ -546,6 +542,21 @@ static void northbridge_init(struct device *dev)
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MCHBAR32(0x5500) = 0x00100001;
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}
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#if CONFIG_EARLY_CBMEM_INIT
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int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size)
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{
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uint32_t tseg;
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/* Put the CBMEM location just below TSEG. */
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*tables_size = HIGH_MEMORY_SIZE;
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tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
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TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE;
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*tables_base = tseg;
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return 0;
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}
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#endif
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static void northbridge_enable(device_t dev)
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{
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#if CONFIG_HAVE_ACPI_RESUME
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