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haswell: cbmem_get_table_location() implementation 

Provide the implemenation of cbmem_get_table_location() so that
cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT
is enabled. The cbmem tables are located just below the TSEG region.

Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2013-02-12 00:46:17 -06:00 committed by Ronald G. Minnich
parent 25fe2d04d5
commit 605ca1bb9c
1 changed files with 15 additions and 4 deletions
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19
src/northbridge/intel/haswell/northbridge.c
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@ -418,10 +418,6 @@ static void mc_add_dram_resources(device_t dev)
mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif #endif
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_size = HIGH_MEMORY_SIZE;
high_tables_base = mc_values[TSEG_REG] - high_tables_size;
} }
static void mc_read_resources(device_t dev) static void mc_read_resources(device_t dev)
@ -546,6 +542,21 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001; MCHBAR32(0x5500) = 0x00100001;
} }
#if CONFIG_EARLY_CBMEM_INIT
int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size)
{
uint32_t tseg;
/* Put the CBMEM location just below TSEG. */
*tables_size = HIGH_MEMORY_SIZE;
tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE;
*tables_base = tseg;
return 0;
}
#endif
static void northbridge_enable(device_t dev) static void northbridge_enable(device_t dev)
{ {
#if CONFIG_HAVE_ACPI_RESUME #if CONFIG_HAVE_ACPI_RESUME