Fix/drop some obsolete comments,

- s/Options.lb/devicetree.cb/
 
 - s/Config.lb/devicetree.cb/

 - s/cache_as_ram_auto.c/romstage.c/
 
 - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
   the tree now.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/mahogany_fam10/spd_addr.h

@@ -19,7 +19,7 @@
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in
- * cache_as_ram_auto.c
+ * romstage.c
  */
 
 #define RC00 0

src/mainboard/amd/norwich/romstage.c

@@ -77,7 +77,7 @@ void main(unsigned long bist)
 	/* cs5536_disable_internal_uart: disable them for now, set them
 	 * up later...
 	 */
-	/* If debug. real setup done in chipset init via Config.lb. */
+	/* If debug. real setup done in chipset init via devicetree.cb. */
 	cs5536_setup_onchipuart(1);
 	mb_gpio_init();
 	uart_init();

src/mainboard/amd/tilapia_fam10/spd_addr.h

@@ -19,7 +19,7 @@
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in
- * cache_as_ram_auto.c
+ * romstage.c
  */
 
 #define RC00 0

src/mainboard/asus/m4a785-m/spd_addr.h

@@ -19,7 +19,7 @@
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in
- * cache_as_ram_auto.c
+ * romstage.c
  */
 
 #define RC00 0

src/mainboard/iei/kino-780am2-fam10/spd_addr.h

@@ -19,7 +19,7 @@
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in
- * cache_as_ram_auto.c
+ * romstage.c
  */
 
 #define RC00 0

src/mainboard/intel/xe7501devkit/acpi_tables.c

@@ -55,7 +55,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	// P64H2#2 Bus A IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
@@ -63,7 +63,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	// P64H2#2 Bus B IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
@@ -72,7 +72,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	// P64H2#1 Bus A IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
@@ -80,7 +80,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	// P64H2#1 Bus B IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;

src/mainboard/intel/xe7501devkit/mptable.c

@@ -42,14 +42,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 	// P64H2#2 Bus A IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#2 Bus B IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
 
@@ -57,14 +57,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 	// P64H2#1 Bus A IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#1 Bus B IOAPIC
 	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
 }

src/mainboard/supermicro/h8dmr_fam10/README

@@ -2,10 +2,6 @@
 
 There are a number of outstanding issues:
 
-* we don't have the mc_patch_01000086.h CPU ucode file yet which is
-referenced in a comment in src/mainboard/supermicro/h8dmr_fam10/Options.lb.
-AMD has not released it yet. This is not a problem specific to this port.
-
 * I'm seeing toolchain issues. I can't get this tree to compile correctly with
 gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
 CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness

src/mainboard/traverse/geos/romstage.c

@@ -78,7 +78,7 @@ void main(unsigned long bist)
 	/* cs5536_disable_internal_uart: disable them for now, set them
 	 * up later...
 	 */
-	/* If debug. real setup done in chipset init via Config.lb. */
+	/* If debug. real setup done in chipset init via devicetree.cb. */
 	cs5536_setup_onchipuart(1);
 	mb_gpio_init();
 	uart_init();

src/mainboard/via/epia-m700/acpi_tables.c

@@ -42,9 +42,9 @@ extern u32 wake_vec;
 
 /*
  * These four macros are copied from <arch/smp/mpspec.h>, I have to do this
- * since the "default CONFIG_GENERATE_MP_TABLE = 0" in Options.lb, and also since
+ * since the "CONFIG_GENERATE_MP_TABLE = 0", and also since
  * mainboard/via/... have no mptable.c (so that I can not set
- * CONFIG_GENERATE_MP_TABLE = 1) as many other mainboards.
+ * "CONFIG_GENERATE_MP_TABLE = 1" as many other mainboards.
  * So I have to copy these four to here. acpi_fill_madt() needs this.
  */
 #define MP_IRQ_POLARITY_HIGH	0x1

src/mainboard/via/epia-n/acpi_tables.c

@@ -39,10 +39,10 @@
 extern const unsigned char AmlCode[];
 
 /*
- * These four macros are copied from <arch/smp/mpspec.h>, I have to do this
+ * These 8 macros are copied from <arch/smp/mpspec.h>, I have to do this
- * since the "default CONFIG_GENERATE_MP_TABLE = 0" in Options.lb, and also since
+ * since the "CONFIG_GENERATE_MP_TABLE = 0", and also since
  * mainboard/via/... have no mptable.c (so that I can not set
- * CONFIG_GENERATE_MP_TABLE = 1) as many other mainboards.
+ * "CONFIG_GENERATE_MP_TABLE = 1" as many other mainboards.
  * So I have to copy these four to here. acpi_fill_madt() needs this.
  */
 #define MP_IRQ_POLARITY_DEFAULT	0x0

src/northbridge/amd/amdk8/northbridge.c

@@ -1,6 +1,6 @@
 /* This should be done by Eric
 	2004.12 yhlu add dual core support
-	2005.01 yhlu add support move apic before pci_domain in MB Config.lb
+	2005.01 yhlu add support move apic before pci_domain in MB devicetree.cb
 	2005.02 yhlu add e0 memory hole support
 	2005.11 yhlu add put sb ht chain on bus 0
 */

src/northbridge/amd/lx/grphinit.c

@@ -85,7 +85,7 @@ void graphics_init(void)
 	 * Controller Priority Select(11)                       1, Primary
 	 * Display Select(10:8)                                         0x0, CRT
 	 * Graphics Memory Size(7:1)                            CONFIG_VIDEO_MB >> 1,
-	 *                                                                                      defined in mainboard/../Options.lb
+	 *                                                                                      defined in devicetree.cb
 	 * PLL Reference Clock Bypass(0)                        0, Default
 	 */
 

src/northbridge/intel/i945/early_init.c

@@ -570,7 +570,7 @@ static void i945_setup_pci_express_x16(void)
 
 	/* Setup SLOTCAP */
 	/* TODO: These values are mainboard dependent and should
-	 * be set from Config.lb or Options.lb.
+	 * be set from devicetree.cb.
 	 */
 	/* NOTE: SLOTCAP becomes RO after the first write! */
 	reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4);

src/southbridge/intel/i82801ax/i82801ax_lpc.c

@@ -68,7 +68,7 @@ typedef struct southbridge_intel_i82801ax_config config_t;
 /*
  * Use 0x0ef8 for a bitmap to cover all these IRQ's.
  * Use the defined IRQ values above or set mainboard
- * specific IRQ values in your mainboards Config.lb.
+ * specific IRQ values in your devicetree.cb.
  */
 static void i82801ax_enable_apic(struct device *dev)
 {

src/southbridge/intel/i82801bx/i82801bx_lpc.c

@@ -70,7 +70,7 @@ typedef struct southbridge_intel_i82801bx_config config_t;
 /*
  * Use 0x0ef8 for a bitmap to cover all these IRQ's.
  * Use the defined IRQ values above or set mainboard
- * specific IRQ values in your mainboards Config.lb.
+ * specific IRQ values in your devicetree.cb.
 */
 static void i82801bx_enable_apic(struct device *dev)
 {

src/southbridge/intel/i82801gx/i82801gx_ide.c

@@ -37,7 +37,7 @@ static void ide_init(struct device *dev)
 
 	printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
 	if (config == NULL) {
-		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
+		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;
 	} else {

src/southbridge/intel/i82801gx/i82801gx_sata.c

@@ -36,7 +36,7 @@ static void sata_init(struct device *dev)
 	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
 
 	if (config == NULL) {
-		printk(BIOS_ERR, "i82801gx_sata: error: device not in Config.lb!\n");
+		printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
 		return;
 	}
 

src/southbridge/intel/i82870/p64h2_ioapic.c

@@ -40,10 +40,10 @@ static void p64h2_ioapic_init(device_t dev)
 
     // A note on IOAPIC addresses:
     //  0 and 1 are used for the local APICs of the dual virtual
-	//	(hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb).
+    //  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
     //  6 and 7 are used for the local APICs of the dual virtual
-	//	(hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb).
+    //  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-    //  2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c)
+    //  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
 
     // Map APIC index into APIC ID
     // IDs 3, 4, 5, and 8+ are available (see above note)