mainboard/variant/puff: set PL values for puff
To be safe for now, don't differentiate between SKUs and use lower values to ensure board won't be browned out. BUG=b:143246320 TEST=none BRANCH=none Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -36,6 +36,11 @@ void __weak variant_ramstage_init(void)
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/* Default weak implementation */
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}
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void __weak variant_mainboard_enable(struct device *dev)
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{
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/* Override mainboard settings per board */
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}
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static void mainboard_init(struct device *dev)
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{
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mainboard_ec_init();
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@ -45,6 +50,7 @@ static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_init;
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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variant_mainboard_enable(dev);
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}
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static void mainboard_chip_init(void *chip_info)
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@ -53,4 +53,7 @@ void variant_devtree_update(void);
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/* Perform variant specific initialization early on in ramstage. */
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void variant_ramstage_init(void);
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/* Perform variant specific mainboard initialization */
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void variant_mainboard_enable(struct device *dev);
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#endif /* BASEBOARD_VARIANTS_H */
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@ -13,4 +13,5 @@
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##
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ramstage-y += gpio.c
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ramstage-y += mainboard.c
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bootblock-y += gpio.c
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@ -0,0 +1,90 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <chip.h>
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#include <device/device.h>
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#include <ec/google/chromeec/ec.h>
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/*
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* For type-C chargers, set PL2 to 90% of max power to account for
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* cable loss and FET Rdson loss in the path from the source.
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*/
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#define SET_PSYSPL2(w) (9 * (w) / 10)
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#define PUFF_PL2 (35)
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#define PUFF_PSYSPL2 (58)
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#define PUFF_MAX_TIME_WINDOW 6
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#define PUFF_MIN_DUTYCYCLE 4
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/*
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* mainboard_set_power_limits
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*
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* Set Pl2 and SysPl2 values based on detected charger.
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* Values are defined below but we use U22 value for all SKUs for now.
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* definitions:
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* x = no value entered. Use default value in parenthesis.
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* will set 0 to anything that shouldn't be set.
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* n = max value of power adapter.
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* +-------------+-----+---------+-----------+-------+
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* | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
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* +-------------+-----+---------+-----------+-------+
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* | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
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* | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
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* +-------------+-----+---------+-----------+-------+
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* For USB C charger:
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* +-------------+-----+---------+---------+-------+
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* | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
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* +-------------+-----+---------+---------+-------+
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* | 60 (U42) | 44 | 54 | 54 | 54 |
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* | 60 (U22) | 29 | 54 | 54 | x(43) |
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* | n (U42) | 44 | .9n | .9n | .9n |
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* | n (U22) | 29 | .9n | .9n | x(43) |
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* +-------------+-----+---------+---------+-------+
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*/
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static void mainboard_set_power_limits(config_t *conf)
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{
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enum usb_chg_type type;
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u32 watts;
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u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
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int rv = google_chromeec_get_usb_pd_power_info(&type, &watts);
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/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
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conf->tdp_psyspl3 = 0;
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conf->tdp_pl4 = 0;
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if (rv == 0 && type == USB_CHG_TYPE_PD) {
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/* Detected USB-PD. Base on max value of adapter */
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psyspl2 = watts;
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conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
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/* set max possible time window */
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conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
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/* set minimum duty cycle */
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conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
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conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
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}
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conf->tdp_pl2_override = PUFF_PL2;
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/* set psyspl2 to 90% of max adapter power */
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conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
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}
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void variant_mainboard_enable(struct device *dev)
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{
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config_t *conf = config_of_soc();
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mainboard_set_power_limits(conf);
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}
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