src/soc/intel: Remove unused <stdlib.h>

Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/cpu.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdlib.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>

src/soc/intel/baytrail/gfx.c

@@ -21,7 +21,6 @@
 #include <device/pci_ids.h>
 #include <drivers/intel/gma/opregion.h>
 #include <reg_script.h>
-#include <stdlib.h>
 #include <soc/gfx.h>
 #include <soc/iosf.h>
 #include <soc/nvs.h>

src/soc/intel/baytrail/ramstage.c

@@ -23,7 +23,6 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <stdlib.h>
 #include <string.h>
 
 #include <soc/gpio.h>

src/soc/intel/baytrail/smihandler.c

@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <console/console.h>

src/soc/intel/braswell/cpu.c

@@ -33,7 +33,6 @@
 #include <soc/msr.h>
 #include <soc/pattrs.h>
 #include <soc/ramstage.h>
-#include <stdlib.h>
 
 /* Core level MSRs */
 static const struct reg_script core_msr_script[] = {

src/soc/intel/braswell/ramstage.c

@@ -37,7 +37,6 @@
 #include <soc/ramstage.h>
 #include <soc/intel/common/acpi.h>
 #include <boardid.h>
-#include <stdlib.h>
 #include <string.h>
 
 #define SHOW_PATTRS 1

src/soc/intel/braswell/smihandler.c

@@ -29,7 +29,6 @@
 #include <soc/pm.h>
 #include <spi-generic.h>
 #include <stdint.h>
-#include <stdlib.h>
 #include <soc/gpio.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */

src/soc/intel/broadwell/finalize.c

@@ -20,7 +20,6 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 #include <spi-generic.h>
-#include <stdlib.h>
 #include <soc/pci_devs.h>
 #include <soc/lpc.h>
 #include <soc/me.h>

src/soc/intel/broadwell/igd.c

@@ -22,7 +22,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
 #include <string.h>
 #include <reg_script.h>
 #include <cbmem.h>

src/soc/intel/broadwell/me_status.c

@@ -16,7 +16,6 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <device/pci.h>
-#include <stdlib.h>
 #include <string.h>
 #include <soc/pci_devs.h>
 #include <soc/me.h>

src/soc/intel/broadwell/minihd.c

@@ -21,7 +21,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/mmio.h>
-#include <stdlib.h>
 #include <soc/intel/common/hda_verb.h>
 #include <soc/ramstage.h>
 #include <soc/igd.h>

src/soc/intel/broadwell/pei_data.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdlib.h>
 #include <stdint.h>
 #include <console/streams.h>
 #include <soc/iomap.h>

src/soc/intel/broadwell/ramstage.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <device/device.h>
-#include <stdlib.h>
 #include <string.h>
 #include <soc/nvs.h>
 #include <soc/pm.h>

src/soc/intel/broadwell/romstage/cpu.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/cpu.h>
-#include <stdlib.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <soc/cpu.h>

src/soc/intel/broadwell/romstage/power_state.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <reg_script.h>
 #include <stdint.h>
-#include <stdlib.h>
 #include <string.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>

src/soc/intel/broadwell/romstage/systemagent.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdlib.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>

src/soc/intel/broadwell/serialio.c

@@ -20,7 +20,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
 #include <soc/iobp.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>

src/soc/intel/broadwell/systemagent.c

@@ -22,7 +22,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>

src/soc/intel/cannonlake/finalize.c

@@ -33,7 +33,6 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <soc/systemagent.h>
-#include <stdlib.h>
 
 #include "chip.h"
 

src/soc/intel/cannonlake/me.c

@@ -22,7 +22,6 @@
 #include <soc/me.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>
-#include <stdlib.h>
 
 /* Miscellaneous constants */
 enum {

src/soc/intel/cannonlake/pmutil.c

@@ -30,7 +30,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/common/acpi_wake_source.c

@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <soc/nvs.h>
 #include <stdint.h>
-#include <stdlib.h>
 #include "acpi.h"
 
 __weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -25,7 +25,6 @@
 #include <soc/pci_devs.h>
 #include <spi_flash.h>
 #include <spi-generic.h>
-#include <stdlib.h>
 
 /*
  * Get the FAST_SPIBAR.

src/soc/intel/common/block/smm/smihandler.c

@@ -38,7 +38,6 @@
 #include <soc/smbus.h>
 #include <spi-generic.h>
 #include <stdint.h>
-#include <stdlib.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */
 static struct global_nvs_t *gnvs;

src/soc/intel/common/block/systemagent/memmap.c

@@ -20,7 +20,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <intelblocks/systemagent.h>
-#include <stdlib.h>
 
 /*
  * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):

src/soc/intel/denverton_ns/csme_ie_kt.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>

src/soc/intel/denverton_ns/smihandler.c

@@ -16,7 +16,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>

src/soc/intel/denverton_ns/systemagent.c

@@ -24,7 +24,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
 #include <timer.h>
 
 #include <soc/iomap.h>

src/soc/intel/icelake/finalize.c

@@ -33,7 +33,6 @@
 #include <soc/smbus.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
-#include <stdlib.h>
 
 #define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
 #define CAMERA2_CLK		0x8080 /* Camera 2 Clock */

src/soc/intel/icelake/pmutil.c

@@ -29,7 +29,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <stdlib.h>
 #include <soc/espi.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/soc/intel/skylake/finalize.c

@@ -38,7 +38,6 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <soc/systemagent.h>
-#include <stdlib.h>
 #include <timer.h>
 
 #include "chip.h"

src/soc/intel/skylake/me.c

@@ -23,7 +23,6 @@
 #include <soc/me.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>
-#include <stdlib.h>
 
 
 /* HFSTS1[3:0] Current Working State Values */

src/soc/intel/skylake/pmutil.c

@@ -29,7 +29,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/tco.h>
-#include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/tigerlake/finalize.c

@@ -39,7 +39,6 @@
 #include <soc/smbus.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
-#include <stdlib.h>
 
 #define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
 #define CAMERA2_CLK		0x8080 /* Camera 2 Clock */

src/soc/intel/tigerlake/pmutil.c

@@ -36,7 +36,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <stdlib.h>
 #include <soc/espi.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>