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mb/google/hatch: Initialize FPMCU_PCH_BOOT1 

In the latest hatch schematics, BOOT1 for the FP MCU is now connected
to the AP.  Configuring it to be the same as BOOT0.

BUG=b:126455006
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max

Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2019-03-26 11:12:56 -07:00 committed by Patrick Georgi
parent 68890b9d59
commit 60aaac7ad0
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/hatch/variants/baseboard/gpio.c
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@ -33,8 +33,8 @@ static const struct pad_config gpio_table[] = {
/* A8 : EMR_GARAGE_DET */ /* A8 : EMR_GARAGE_DET */
PAD_CFG_GPI_GPIO_DRIVER(GPP_A8, NONE, DEEP), PAD_CFG_GPI_GPIO_DRIVER(GPP_A8, NONE, DEEP),
/* A9 : ESPI_CLK */ /* A9 : ESPI_CLK */
/* A10 : PEN_RESET_ODL */ /* A10 : FPMCU_PCH_BOOT1 */
PAD_NC(GPP_A10, NONE), PAD_CFG_GPO(GPP_A10, 0, DEEP),
/* A11 : PCH_SPI_FPMCU_CS_L */ /* A11 : PCH_SPI_FPMCU_CS_L */
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
/* A12 : FPMCU_RST_ODL */ /* A12 : FPMCU_RST_ODL */