diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
index 7af613bb39..d8e78072fd 100644
--- a/src/mainboard/lenovo/x201/smihandler.c
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -25,7 +25,7 @@
 #include "southbridge/intel/ibexpeak/nvs.h"
 #include "southbridge/intel/ibexpeak/pch.h"
 #include "southbridge/intel/ibexpeak/me.h"
-#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/nehalem/nehalem.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
 #include <ec/acpi/ec.h>
 #include <pc80/mc146818rtc.h>
@@ -164,7 +164,7 @@ int mainboard_smi_apmc(u8 data)
 
 		intel_me_finalize_smm();
 		intel_pch_finalize_smm();
-		intel_sandybridge_finalize_smm();
+		intel_nehalem_finalize_smm();
 		intel_model_2065x_finalize_smm();
 
 		mainboard_finalized = 1;
diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c
index f04ff9028b..bbe1597688 100644
--- a/src/mainboard/packardbell/ms2290/smihandler.c
+++ b/src/mainboard/packardbell/ms2290/smihandler.c
@@ -25,7 +25,7 @@
 #include "southbridge/intel/ibexpeak/nvs.h"
 #include "southbridge/intel/ibexpeak/pch.h"
 #include "southbridge/intel/ibexpeak/me.h"
-#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/nehalem/nehalem.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
 #include <ec/acpi/ec.h>
 #include <pc80/mc146818rtc.h>
@@ -88,7 +88,7 @@ int mainboard_smi_apmc(u8 data)
 
 		intel_me_finalize_smm();
 		intel_pch_finalize_smm();
-		intel_sandybridge_finalize_smm();
+		intel_nehalem_finalize_smm();
 		intel_model_2065x_finalize_smm();
 
 		mainboard_finalized = 1;
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index 401d9ecb99..72baa4869b 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -24,7 +24,7 @@
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
 
-void intel_sandybridge_finalize_smm(void)
+void intel_nehalem_finalize_smm(void)
 {
 	pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);	/* GGC */
 	pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);	/* DPR */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index b90e5a910d..2218433b7d 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -593,7 +593,7 @@ struct ied_header {
 #define PCI_DEVICE_ID_IB 0x0154
 
 #ifdef __SMM__
-void intel_sandybridge_finalize_smm(void);
+void intel_nehalem_finalize_smm(void);
 #else /* !__SMM__ */
 int bridge_silicon_revision(void);
 void nehalem_early_initialization(int chipset_type);