soc/intel: Kconfig: Correct UART source clock value in comment

Correct UART source clock value in comment from 120 MHz to 100 MHz.

BUG=b:249530903

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/Kconfig

@@ -338,7 +338,7 @@ config VBT_DATA_SIZE_KB
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
-# ADL UART source clock: 120MHz
+# ADL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
 	default 0x25a

src/soc/intel/elkhartlake/Kconfig

@@ -171,7 +171,7 @@ config CONSOLE_UART_BASE_ADDRESS
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
-# EHL UART source clock: 120MHz
+# EHL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
 	default 0x25a

src/soc/intel/meteorlake/Kconfig

@@ -238,7 +238,7 @@ config VBT_DATA_SIZE_KB
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
-# MTL UART source clock: 120MHz
+# MTL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
 	default 0x25a

src/soc/intel/tigerlake/Kconfig

@@ -219,7 +219,7 @@ config CONSOLE_UART_BASE_ADDRESS
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
-# TGL UART source clock: 120MHz
+# TGL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
 	default 0x25a