soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC option
The SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option is valid for all SoCs with Zen-based CPU cores including the family 1Ah, so remove the suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58d29e69a44b7b97fa5cfeb0e461531b926f7480 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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@ -65,7 +65,7 @@ config SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SVI2
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select SOC_AMD_COMMON_BLOCK_SVI2
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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@ -96,15 +96,15 @@ config SOC_AMD_COMMON_BLOCK_SVI3
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Select this option is the SoC uses the serial VID 3 standard for
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Select this option is the SoC uses the serial VID 3 standard for
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encoding the voltage it requests from the VRM.
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encoding the voltage it requests from the VRM.
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config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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config SOC_AMD_COMMON_BLOCK_TSC
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bool
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bool
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select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function
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select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function
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select TSC_SYNC_LFENCE
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select TSC_SYNC_LFENCE
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select UDELAY_TSC
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select UDELAY_TSC
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help
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help
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Select this option to add the common functions for getting the TSC
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Select this option to add the common functions for getting the TSC
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frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC-
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frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide
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based monotonic timer functionality to the build.
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TSC-based monotonic timer functionality to the build.
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config SOC_AMD_COMMON_BLOCK_UCODE
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config SOC_AMD_COMMON_BLOCK_UCODE
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bool
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bool
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@ -20,7 +20,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y)
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC),y)
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bootblock-y += tsc_freq.c
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bootblock-y += tsc_freq.c
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bootblock-y += monotonic_timer.c
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bootblock-y += monotonic_timer.c
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@ -37,4 +37,4 @@ ramstage-y += monotonic_timer.c
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smm-y += tsc_freq.c
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smm-y += tsc_freq.c
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smm-y += monotonic_timer.c
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smm-y += monotonic_timer.c
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC
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@ -71,7 +71,7 @@ config SOC_AMD_GLINDA
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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@ -73,7 +73,7 @@ config SOC_AMD_REMBRANDT_BASE
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_STB
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select SOC_AMD_COMMON_BLOCK_STB
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_XHCI
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select SOC_AMD_COMMON_BLOCK_XHCI
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@ -71,7 +71,7 @@ config SOC_AMD_PHOENIX
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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@ -61,7 +61,7 @@ config SOC_AMD_PICASSO
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SVI2
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select SOC_AMD_COMMON_BLOCK_SVI2
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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