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patches from Yh Lu. Tested and working on HDAMA 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2003-08-04 22:13:57 +00:00
parent a43048d371
commit 60e185fcc4
11 changed files with 354 additions and 68 deletions
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29
src/cpu/k8/cpufixup.c
View File

@ -32,15 +32,28 @@ void k8_cpufixup(struct mem_range *mem)
mmio_basek = tomk;
}
/* Setup TOP_MEM */
msr.hi = mmio_basek >> 22;
msr.lo = mmio_basek << 10;
wrmsr(TOP_MEM, msr);
#if 1
/* Report the amount of memory. */
print_debug("cpufixup RAM: 0x");
print_debug_hex32(tomk);
print_debug(" KB\r\n");
#endif
/* Now set top of memory */
msr.lo = (tomk & 0x003fffff) << 10;
msr.hi = (tomk & 0xffc00000) >> 22;
wrmsr(TOP_MEM2, msr);
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
* so I can see my rom chip and other I/O devices.
*/
if (tomk >= 0x003f0000) {
tomk = 0x3f0000;
} // tom_k = 0x3c0000;
msr.lo = (tomk & 0x003fffff) << 10;
msr.hi = (tomk & 0xffc00000) >> 22;
wrmsr(TOP_MEM, msr);
/* Setup TOP_MEM2 */
msr.hi = tomk >> 22;
msr.lo = tomk << 10;
wrmsr(TOP_MEM2, msr);
/* zero the IORR's before we enable to prevent
* undefined side effects.

54
src/include/console/console.h
View File

@ -92,34 +92,34 @@ int do_printk(int msg_level, const char *fmt, ...);
#define print_debug_char(CH) printk_debug ("%c", (CH))
#define print_spew_char(CH) printk_spew ("%c", (CH))
#define print_emerg_hex8(HEX) printk_emerg ("%08x", (HEX))
#define print_alert_hex8(HEX) printk_alert ("%08x", (HEX))
#define print_crit_hex8(HEX) printk_crit ("%08x", (HEX))
#define print_err_hex8(HEX) printk_err ("%08x", (HEX))
#define print_warning_hex8(HEX) printk_warning("%08x", (HEX))
#define print_notice_hex8(HEX) printk_notice ("%08x", (HEX))
#define print_info_hex8(HEX) printk_info ("%08x", (HEX))
#define print_debug_hex8(HEX) printk_debug ("%08x", (HEX))
#define print_spew_hex8(HEX) printk_spew ("%08x", (HEX))
#define print_emerg_hex8(HEX) printk_emerg ("%02x", (HEX))
#define print_alert_hex8(HEX) printk_alert ("%02x", (HEX))
#define print_crit_hex8(HEX) printk_crit ("%02x", (HEX))
#define print_err_hex8(HEX) printk_err ("%02x", (HEX))
#define print_warning_hex8(HEX) printk_warning("%02x", (HEX))
#define print_notice_hex8(HEX) printk_notice ("%02x", (HEX))
#define print_info_hex8(HEX) printk_info ("%02x", (HEX))
#define print_debug_hex8(HEX) printk_debug ("%02x", (HEX))
#define print_spew_hex8(HEX) printk_spew ("%02x", (HEX))
#define print_emerg_hex16(HEX) printk_emerg ("%016x", (HEX))
#define print_alert_hex16(HEX) printk_alert ("%016x", (HEX))
#define print_crit_hex16(HEX) printk_crit ("%016x", (HEX))
#define print_err_hex16(HEX) printk_err ("%016x", (HEX))
#define print_warning_hex16(HEX) printk_warning("%016x", (HEX))
#define print_notice_hex16(HEX) printk_notice ("%016x", (HEX))
#define print_info_hex16(HEX) printk_info ("%016x", (HEX))
#define print_debug_hex16(HEX) printk_debug ("%016x", (HEX))
#define print_spew_hex16(HEX) printk_spew ("%016x", (HEX))
#define print_emerg_hex16(HEX) printk_emerg ("%04x", (HEX))
#define print_alert_hex16(HEX) printk_alert ("%04x", (HEX))
#define print_crit_hex16(HEX) printk_crit ("%04x", (HEX))
#define print_err_hex16(HEX) printk_err ("%04x", (HEX))
#define print_warning_hex16(HEX) printk_warning("%04x", (HEX))
#define print_notice_hex16(HEX) printk_notice ("%04x", (HEX))
#define print_info_hex16(HEX) printk_info ("%04x", (HEX))
#define print_debug_hex16(HEX) printk_debug ("%04x", (HEX))
#define print_spew_hex16(HEX) printk_spew ("%04x", (HEX))
#define print_emerg_hex32(HEX) printk_emerg ("%032x", (HEX))
#define print_alert_hex32(HEX) printk_alert ("%032x", (HEX))
#define print_crit_hex32(HEX) printk_crit ("%032x", (HEX))
#define print_err_hex32(HEX) printk_err ("%032x", (HEX))
#define print_warning_hex32(HEX) printk_warning("%032x", (HEX))
#define print_notice_hex32(HEX) printk_notice ("%032x", (HEX))
#define print_info_hex32(HEX) printk_info ("%032x", (HEX))
#define print_debug_hex32(HEX) printk_debug ("%032x", (HEX))
#define print_spew_hex32(HEX) printk_spew ("%032x", (HEX))
#define print_emerg_hex32(HEX) printk_emerg ("%08x", (HEX))
#define print_alert_hex32(HEX) printk_alert ("%08x", (HEX))
#define print_crit_hex32(HEX) printk_crit ("%08x", (HEX))
#define print_err_hex32(HEX) printk_err ("%08x", (HEX))
#define print_warning_hex32(HEX) printk_warning("%08x", (HEX))
#define print_notice_hex32(HEX) printk_notice ("%08x", (HEX))
#define print_info_hex32(HEX) printk_info ("%08x", (HEX))
#define print_debug_hex32(HEX) printk_debug ("%08x", (HEX))
#define print_spew_hex32(HEX) printk_spew ("%08x", (HEX))
#endif /* CONSOLE_CONSOLE_H_ */

4
src/mainboard/arima/hdama/Config.lb
View File

@ -154,9 +154,9 @@ superio NSC/pc87360
register "com1" = "{1}"
register "lpt" = "{1}"
end
# dir /pc80
dir /pc80
##dir /src/superio/winbond/w83627hf
dir /cpu/k8
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
end

6
src/mainboard/tyan/s2880/Config.lb
View File

@ -16,11 +16,13 @@ uses ARCH
### Build the objects we have code for in this directory.
###
##object mainboard.o
#config chip.h
#register "fixup_scsi" = "1"
config chip.h
register "fixup_scsi" = "1"
driver mainboard.o
driver lsi_scsi.o
driver adaptec_scsi.o
driver intel_nic.o
object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end

2
src/mainboard/tyan/s2880/auto.c
View File

@ -14,7 +14,7 @@
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
//#include "debug.c"
static void memreset_setup(void)
{

2
src/mainboard/tyan/s2880/chip.h
View File

@ -1,3 +1,5 @@
extern struct chip_control mainboard_tyan_s2880_control;
struct mainboard_tyan_s2880_config {
int fixup_scsi;
};

8
src/mainboard/tyan/s2880/irq_tables.c
View File

@ -18,20 +18,20 @@ const struct irq_routing_table intel_irq_routing_table = {
0x746b, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xe8, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
0x37, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
{0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
{0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
{0x1,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
{0x1,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x3,0x8, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
{0x1,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x1,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
{0x2,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
}
};

64
src/mainboard/tyan/s2880/mainboard.c
View File

@ -1,10 +1,10 @@
#include <console/console.h>
#include <device/device.h>
//#include <device/chip.h>
#include <device/chip.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
//#include "chip.h"
#include "chip.h"
//#include <part/mainboard.h>
//#include "lsi_scsi.c"
unsigned long initial_apicid[MAX_CPUS] =
@ -35,8 +35,9 @@ static void fixup_lsi_53c1030(struct device *pdev)
// lsi_scsi_init(pdev);
}
*/
//extern static void lsi_scsi_init(struct device *dev);
static void print_pci_regs(struct device *dev)
/*static void print_pci_regs(struct device *dev)
{
uint8_t byte;
int i;
@ -55,12 +56,13 @@ static void print_pci_regs(struct device *dev)
*/
static void onboard_scsi_fixup(void)
{
struct device *dev;
/*
// Set the scsi device id's
// struct device *dev;
/* // Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",0,1,0);
dev = dev_find_slot(0, PCI_DEVFN(0x1, 0));
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",0,2,0);
@ -68,32 +70,46 @@ static void onboard_scsi_fixup(void)
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",1,0xa,0);
dev = dev_find_slot(1, PCI_DEVFN(0xa, 0));
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",1,0xa,1);
dev = dev_find_slot(1, PCI_DEVFN(0xa, 1));
printk_debug("%2d:%2d:%2d\n",0,3,0);
dev = dev_find_slot(0, PCI_DEVFN(0x3, 0));
if (dev) {
print_pci_regs(dev);
}
printk_debug("%2d:%2d:%2d\n",1,9,0);
dev = dev_find_slot(1, PCI_DEVFN(0x9, 0));
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",1,0x7,0);
dev = dev_find_slot(1, PCI_DEVFN(0x7, 0));
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",1,9,1);
dev = dev_find_slot(1, PCI_DEVFN(0x9, 1));
printk_debug("%2d:%2d:%2d\n",1,0x8,0);
dev = dev_find_slot(1, PCI_DEVFN(0x8, 0));
if (dev) {
print_pci_regs(dev);
}
printk_debug("%2d:%2d:%2d\n",2,3,0);
dev = dev_find_slot(2, PCI_DEVFN(0x3, 0));
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",2,6,0);
dev = dev_find_slot(2, PCI_DEVFN(0x6, 0));
if (dev) {
print_pci_regs(dev);
}
// Set the scsi device id's
printk_debug("%2d:%2d:%2d\n",3,4,0);
dev = dev_find_slot(3, PCI_DEVFN(0x4, 0));
if (dev) {
print_pci_regs(dev);
}
*/
/*
dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
if(!dev) {
@ -105,7 +121,7 @@ static void onboard_scsi_fixup(void)
*/
}
/*
static void
enable(struct chip *chip, enum chip_pass pass)
{
@ -116,7 +132,7 @@ enable(struct chip *chip, enum chip_pass pass)
switch (pass) {
default: break;
case CONF_PASS_PRE_BOOT:
if (conf->fixup_scsi)
if (conf->fixup_scsi)
onboard_scsi_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
pass);
@ -132,7 +148,7 @@ void final_mainboard_fixup(void)
}
struct chip_control mainboard_tyan_s2880_control = {
enable: enable,
name: "Tyan s2880 mainboard "
.enable= enable,
.name= "Tyan s2880 mainboard "
};
*/

38
src/mainboard/tyan/s2880/mptable.c
View File

@ -71,13 +71,51 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xf, 0x2, 0xf);
//On Board AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13);
//On Board ATI Display Adapter
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x2, 0x12);
//Slot 5 PCI 32
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x10, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x11, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x12, 0x2, 0x12); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x13, 0x2, 0x13); //
//On Board Promise Serial ATA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x14, 0x2, 0x11);
//Slot 3 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);//
//Slot 4 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);//
//On Board NIC and LSI scsi
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x25, 0x3, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x28, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x29, 0x3, 0x1);
//Slot 1 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); //
//Slot 2 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);//
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);

20
src/northbridge/amd/amdk8/raminit.c
View File

@ -1124,6 +1124,23 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
}
}
//BY LYH //Fill next base reg with right value
static void fill_last(unsigned long node_id,unsigned long base)
{
unsigned i;
unsigned base_reg;
base &=0xffff0000;
device_t device;
for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
+= PCI_DEV(0, 1, 0)) {
for(i=node_id+1;i<=7;i++) {
base_reg=0x40+(i<<3);
pci_write_config32(device,base_reg,base);
}
}
}
//BY LYH END
static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned long base_k, unsigned long limit_k)
{
@ -1276,6 +1293,9 @@ static void order_dimms(const struct mem_controller *ctrl)
print_debug("\r\n");
#endif
route_dram_accesses(ctrl, base_k, tom_k);
//BY LYH
fill_last(ctrl->node_id, tom_k<<2);
//BY LYH END
set_top_mem(tom_k);
}

195
targets/tyan/s2880/Config.lb Normal file
View File

@ -0,0 +1,195 @@
# Sample config file for
# the Tyan s2880
# This will make a target directory of ./s2880
loadoptions
target s2880
uses AMD8111_DEV
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses ENABLE_FIXED_AND_VARIABLE_MTRRS
uses FALLBACK_SIZE
uses FINAL_MAINBOARD_FIXUP
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses i586
uses i686
uses INTEL_PPRO_MTRR
uses HEAP_SIZE
uses IRQ_SLOT_COUNT
uses k7
uses k8
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAX_CPUS
uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses _ROMBASE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
uses SIO_BASE
uses SIO_SYSTEM_CLK_INPUT
uses STACK_SIZE
uses USE_ELF_BOOT
uses USE_FALLBACK_IMAGE
uses USE_NORMAL_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
option HAVE_OPTION_TABLE=1
option HAVE_MP_TABLE=1
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0
option i686=1
option i586=1
option INTEL_PPRO_MTRR=1
option k7=1
option k8=1
option ROM_SIZE=524288
# use the new chip configure code.
option CONFIG_CHIP_CONFIGURE=1
### Customize our winbond superio chip for this motherboard
###
option SIO_BASE=0x2e
option SIO_SYSTEM_CLK_INPUT=0
#
###
### Build code to export a programmable irq routing table
###
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=13
#
###
### Build code for SMP support
### Only worry about 2 micro processors
###
option CONFIG_SMP=1
option MAX_CPUS=2
#
###
### Build code to setup a generic IOAPIC
###
option CONFIG_IOAPIC=1
#
###
### MEMORY_HOLE instructs earlymtrr.inc to
### enable caching from 0-640KB and to disable
### caching from 640KB-1MB using fixed MTRRs
###
### Enabling this option breaks SMP because secondary
### CPU identification depends on only variable MTRRs
### being enabled.
###
option MEMORY_HOLE=0
#
###
### Enable both fixed and variable MTRRS
### When we setup MTRRs in mtrr.c
###
### We must setup the fixed mtrrs or we confuse SMP secondary
### processor identification
###
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
#
###
### Clean up the motherboard id strings
###
#option MAINBOARD_PART_NUMBER="Solo7"
#option MAINBOARD_VENDOR="AMD"
#
###
### Call the final_mainboard_fixup function
###
option FINAL_MAINBOARD_FIXUP=1
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
###
### Compute where this copy of linuxBIOS will start in the boot rom
###
#
###
### Compute a range of ROM that can cached to speed up linuxBIOS,
### execution speed.
###
##expr XIP_ROM_SIZE = 65536
##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
##option XIP_ROM_SIZE=65536
##option XIP_ROM_BASE=0xffff0000
#
## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
##option XIP_ROM_SIZE=0x8000
##option XIP_ROM_BASE=0xffff8000
## We don't use compressed image
option CONFIG_COMPRESS=0
option USE_ELF_BOOT=1
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=65536
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000
##
## Use a 64K stack
##
option STACK_SIZE=0x10000
##
## Use a 64K heap
##
option HEAP_SIZE=0x10000
#
###
### Compute the start location and size size of
### The linuxBIOS bootloader.
###
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option CONFIG_ROM_STREAM = 1
option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
#
# Arima hdama
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
option ROM_SECTION_OFFSET= 0
mainboard tyan/s2880
payload ../eepro100.ebi
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option HAVE_FALLBACK_BOOT=1
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
mainboard tyan/s2880
payload ../eepro100.ebi
end
buildrom ROM_SIZE "normal" "fallback"