mediatek/mt8183: add PLL and clock init support

Add PLL and clock init code.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Checked with frequency meter in SOC.

Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/27031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/soc/mediatek/mt8183/Makefile.inc

@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
 
 bootblock-y += bootblock.c
 bootblock-y += ../common/mmu_operations.c mmu_operations.c
+bootblock-y += ../common/pll.c pll.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += ../common/timer.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)

src/soc/mediatek/mt8183/bootblock.c

@@ -15,10 +15,12 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/pll.h>
 #include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	mt_pll_init();
 	mtk_wdt_init();
 }

src/soc/mediatek/mt8183/include/soc/addressmap.h

@@ -23,10 +23,12 @@ enum {
 };
 
 enum {
+	CKSYS_BASE		= IO_PHYS,
 	INFRACFG_AO_BASE	= IO_PHYS + 0x00001000,
 	SPM_BASE		= IO_PHYS + 0x00006000,
 	RGU_BASE                = IO_PHYS + 0x00007000,
 	GPT_BASE		= IO_PHYS + 0x00008000,
+	APMIXED_BASE		= IO_PHYS + 0x0000C000,
 	UART0_BASE		= IO_PHYS + 0x01002000,
 	SMI_BASE		= IO_PHYS + 0x04019000,
 };

src/soc/mediatek/mt8183/include/soc/pll.h

@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_PLL_H
+#define SOC_MEDIATEK_MT8183_PLL_H
+
+#include <types.h>
+#include <soc/pll_common.h>
+
+struct mtk_topckgen_regs {
+	u32 clk_mode;
+	u32 clk_cfg_update;
+	u32 clk_cfg_update1;
+	u32 reserved1[13];
+	u32 clk_cfg_0;
+	u32 clk_cfg_0_set;
+	u32 clk_cfg_0_clr;
+	u32 reserved2[1];
+	u32 clk_cfg_1;
+	u32 clk_cfg_1_set;
+	u32 clk_cfg_1_clr;
+	u32 reserved3[1];
+	u32 clk_cfg_2;
+	u32 clk_cfg_2_set;
+	u32 clk_cfg_2_clr;
+	u32 reserved4[1];
+	u32 clk_cfg_3;
+	u32 clk_cfg_3_set;
+	u32 clk_cfg_3_clr;
+	u32 reserved5[1];
+	u32 clk_cfg_4;
+	u32 clk_cfg_4_set;
+	u32 clk_cfg_4_clr;
+	u32 reserved6[1];
+	u32 clk_cfg_5;
+	u32 clk_cfg_5_set;
+	u32 clk_cfg_5_clr;
+	u32 reserved7[1];
+	u32 clk_cfg_6;
+	u32 clk_cfg_6_set;
+	u32 clk_cfg_6_clr;
+	u32 reserved8[1];
+	u32 clk_cfg_7;
+	u32 clk_cfg_7_set;
+	u32 clk_cfg_7_clr;
+	u32 reserved9[1];
+	u32 clk_cfg_8;
+	u32 clk_cfg_8_set;
+	u32 clk_cfg_8_clr;
+	u32 reserved10[1];
+	u32 clk_cfg_9;
+	u32 clk_cfg_9_set;
+	u32 clk_cfg_9_clr;
+	u32 reserved11[1];
+	u32 clk_cfg_10;
+	u32 clk_cfg_10_set;
+	u32 clk_cfg_10_clr;
+	u32 reserved12[6];
+	u32 clk_misc_cfg_0;
+	u32 clk_misc_cfg_1;
+	u32 clk_dbg_cfg;
+	u32 reserved13[60];
+	u32 clk_scp_cfg_0;
+	u32 clk_scp_cfg_1;
+	u32 reserved14[6];
+	u32 clk26cali_0;
+	u32 clk26cali_1;
+	u32 reserved15[2];
+	u32 cksta_reg;
+	u32 cksta_reg1;
+	u32 reserved16[50];
+	u32 clkmon_clk_sel_reg;
+	u32 clkmon_k1_reg;
+	u32 reserved17[6];
+	u32 clk_auddiv_0;
+	u32 clk_auddiv_1;
+	u32 clk_auddiv_2;
+	u32 aud_top_cfg;
+	u32 aud_top_mon;
+	u32 clk_auddiv_3;
+	u32 reserved18[50];
+	u32 clk_pdn_reg;
+	u32 reserved19[63];
+	u32 clk_extck_reg;
+	u32 reserved20[79];
+	u32 clk_cfg_20;
+	u32 clk_cfg_20_set;
+	u32 clk_cfg_20_clr;
+};
+
+check_member(mtk_topckgen_regs, clk_cfg_0, 0x0040);
+check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0104);
+check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200);
+check_member(mtk_topckgen_regs, clk26cali_0, 0x0220);
+check_member(mtk_topckgen_regs, cksta_reg, 0x0230);
+check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x0300);
+check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320);
+check_member(mtk_topckgen_regs, clk_pdn_reg, 0x0400);
+check_member(mtk_topckgen_regs, clk_extck_reg, 0x0500);
+check_member(mtk_topckgen_regs, clk_cfg_20, 0x0640);
+check_member(mtk_topckgen_regs, clk_cfg_20_clr, 0x0648);
+
+struct mtk_apmixed_regs {
+	u32 ap_pll_con0;
+	u32 ap_pll_con1;
+	u32 ap_pll_con2;
+	u32 ap_pll_con3;
+	u32 ap_pll_con4;
+	u32 ap_pll_con5;
+	u32 ap_pll_con6;
+	u32 ap_pll_con7;
+	u32 ap_pll_con8;
+	u32 clksq_stb_con0;
+	u32 pll_pwr_con0;
+	u32 pll_pwr_con1;
+	u32 pll_iso_con0;
+	u32 pll_iso_con1;
+	u32 pll_stb_con0;
+	u32 div_stb_con0;
+	u32 pll_chg_con0;
+	u32 pll_test_con0;
+	u32 pll_test_con1;
+	u32 reserved1[109];
+	u32 armpll_ll_con0;
+	u32 armpll_ll_con1;
+	u32 armpll_ll_con2;
+	u32 armpll_ll_pwr_con0;
+	u32 armpll_l_con0;
+	u32 armpll_l_con1;
+	u32 armpll_l_con2;
+	u32 armpll_l_pwr_con0;
+	u32 mainpll_con0;
+	u32 mainpll_con1;
+	u32 mainpll_con2;
+	u32 mainpll_pwr_con0;
+	u32 univpll_con0;
+	u32 univpll_con1;
+	u32 univpll_con2;
+	u32 univpll_pwr_con0;
+	u32 mfgpll_con0;
+	u32 mfgpll_con1;
+	u32 mfgpll_con2;
+	u32 mfgpll_pwr_con0;
+	u32 msdcpll_con0;
+	u32 msdcpll_con1;
+	u32 msdcpll_con2;
+	u32 msdcpll_pwr_con0;
+	u32 tvdpll_con0;
+	u32 tvdpll_con1;
+	u32 tvdpll_con2;
+	u32 tvdpll_pwr_con0;
+	u32 mmpll_con0;
+	u32 mmpll_con1;
+	u32 mmpll_con2;
+	u32 mmpll_pwr_con0;
+	u32 mpll_con0;
+	u32 mpll_con1;
+	u32 mpll_con2;
+	u32 mpll_pwr_con0;
+	u32 ccipll_con0;
+	u32 ccipll_con1;
+	u32 ccipll_con2;
+	u32 ccipll_pwr_con0;
+	u32 apll1_con0;
+	u32 apll1_con1;
+	u32 apll1_con2;
+	u32 apll1_con3;
+	u32 apll1_pwr_con0;
+	u32 apll2_con0;
+	u32 apll2_con1;
+	u32 apll2_con2;
+	u32 apll2_con3;
+	u32 apll2_pwr_con0;
+	u32 reserved2[78];
+	u32 ap_auxadc_con0;
+	u32 ap_auxadc_con1;
+	u32 ap_auxadc_con2;
+	u32 ap_auxadc_con3;
+	u32 ap_auxadc_con4;
+	u32 ap_auxadc_con5;
+	u32 reserved3[122];
+	u32 ts_con0;
+	u32 ts_con1;
+	u32 ts_con2;
+	u32 reserved4[61];
+	u32 ulposc_con0;
+	u32 ulposc_con1;
+	u32 ulposc2_con0;
+	u32 ulposc2_con1;
+	u32 reserved5[60];
+	u32 ap_abist_mon_con0;
+	u32 ap_abist_mon_con1;
+	u32 ap_abist_mon_con2;
+	u32 ap_abist_mon_con3;
+	u32 occscan_con0;
+	u32 clkdiv_con0;
+	u32 occscan_con1;
+	u32 occscan_con2;
+	u32 mcu_occscan_con0;
+	u32 reserved6[55];
+	u32 rsv_rw0_con0;
+	u32 rsv_rw1_con0;
+	u32 rsv_ro_con0;
+};
+
+check_member(mtk_apmixed_regs, armpll_ll_con0, 0x0200);
+check_member(mtk_apmixed_regs, ap_auxadc_con0, 0x0400);
+check_member(mtk_apmixed_regs, ts_con0, 0x0600);
+check_member(mtk_apmixed_regs, ulposc_con0, 0x0700);
+check_member(mtk_apmixed_regs, ap_abist_mon_con0, 0x0800);
+check_member(mtk_apmixed_regs, rsv_rw0_con0, 0x0900);
+check_member(mtk_apmixed_regs, rsv_ro_con0, 0x0908);
+
+enum {
+	DIV_MASK = 0x1f << 17,
+	DIV_1 = 0x8 << 17,
+	DIV_2 = 0xa << 17,
+
+	MUX_MASK = 0x3 << 9,
+	MUX_SRC_ARMPLL = 0x1 << 9,
+};
+
+enum {
+	PLL_PWR_ON_DELAY = 30,
+	PLL_ISO_DELAY = 1,
+	PLL_EN_DELAY = 20,
+};
+
+enum {
+	PCW_INTEGER_BITS = 8,
+};
+
+/* PLL rate */
+enum {
+	ARMPLL_LL_HZ	= 1100 * MHz,
+	ARMPLL_L_HZ	= 1200 * MHz,
+	CCIPLL_HZ	= 598 * 2 * MHz,
+	MAINPLL_HZ	= 1092 * MHz,
+	UNIVPLL_HZ	= 1248UL * 2 * MHz,
+	MSDCPLL_HZ	= 384 * MHz,
+	MMPLL_HZ	= 3150UL * MHz,
+	MFGPLL_HZ	= 512 * MHz,
+	TVDPLL_HZ	= 594 * MHz,
+	APLL1_HZ	= 180633600,
+	APLL2_HZ	= 196608 * KHz,
+};
+
+/* top_div rate */
+enum {
+	CLK26M_HZ	= 26 * MHz,
+};
+
+#endif /* SOC_MEDIATEK_MT8183_PLL_H */

src/soc/mediatek/mt8183/pll.c

@@ -0,0 +1,351 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <delay.h>
+#include <stddef.h>
+
+#include <soc/addressmap.h>
+#include <soc/infracfg.h>
+#include <soc/mcucfg.h>
+#include <soc/pll.h>
+
+enum mux_id {
+	TOP_AXI_SEL = 0,
+	TOP_MM_SEL,
+	TOP_IMG_SEL,
+	TOP_CAM_SEL,
+	TOP_DSP_SEL,
+	TOP_DSP1_SEL,
+	TOP_DSP2_SEL,
+	TOP_IPU_IF_SEL,
+	TOP_MFG_SEL,
+	TOP_MFG_52M_SEL,
+	TOP_CAMTG_SEL,
+	TOP_CAMTG2_SEL,
+	TOP_CAMTG3_SEL,
+	TOP_CAMTG4_SEL,
+	TOP_UART_SEL,
+	TOP_SPI_SEL,
+	TOP_MSDC50_0_HCLK_SEL,
+	TOP_MSDC50_0_SEL,
+	TOP_MSDC30_1_SEL,
+	TOP_MSDC30_2_SEL,
+	TOP_AUDIO_SEL,
+	TOP_AUD_INTBUS_SEL,
+	TOP_PMICSPI_SEL,
+	TOP_PWRAP_ULPOSC_SEL,
+	TOP_ATB_SEL,
+	TOP_PWRMCU_SEL,
+	TOP_DPI0_SEL,
+	TOP_SCAM_SEL,
+	TOP_DISP_PWM_SEL,
+	TOP_USB_TOP_SEL,
+	TOP_SSUSB_XHCI_SEL,
+	TOP_SPM_SEL,
+	TOP_I2C_SEL,
+	TOP_SCP_SEL,
+	TOP_SENINF_SEL,
+	TOP_DXCC_SEL,
+	TOP_AUD_ENGEN1_SEL,
+	TOP_AUD_ENGEN2_SEL,
+	TOP_AES_UFSFDE_SEL,
+	TOP_UFS_SEL,
+	TOP_AUD_1_SEL,
+	TOP_AUD_2_SEL,
+	TOP_NR_MUX
+};
+
+#define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)	\
+	[_id] = {							\
+		.reg = &mtk_topckgen->_reg,				\
+		.mux_shift = _mux_shift,				\
+		.mux_width = _mux_width,				\
+		.upd_reg = &mtk_topckgen->_upd_reg,			\
+		.upd_shift = _upd_shift,				\
+	}
+
+static const struct mux muxes[] = {
+	/* CLK_CFG_0 */
+	MUX(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0),
+	MUX(TOP_MM_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1),
+	MUX(TOP_IMG_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
+	MUX(TOP_CAM_SEL, clk_cfg_0, 24, 4, clk_cfg_update, 3),
+	/* CLK_CFG_1 */
+	MUX(TOP_DSP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
+	MUX(TOP_DSP1_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
+	MUX(TOP_DSP2_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
+	MUX(TOP_IPU_IF_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
+	/* CLK_CFG_2 */
+	MUX(TOP_MFG_SEL, clk_cfg_2, 0, 2, clk_cfg_update, 8),
+	MUX(TOP_MFG_52M_SEL, clk_cfg_2, 8, 2, clk_cfg_update, 9),
+	MUX(TOP_CAMTG_SEL, clk_cfg_2, 16, 3, clk_cfg_update, 10),
+	MUX(TOP_CAMTG2_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
+	/* CLK_CFG_3 */
+	MUX(TOP_CAMTG3_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
+	MUX(TOP_CAMTG4_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
+	MUX(TOP_UART_SEL, clk_cfg_3, 16, 1, clk_cfg_update, 14),
+	MUX(TOP_SPI_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15),
+	/* CLK_CFG_4 */
+	MUX(TOP_MSDC50_0_HCLK_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16),
+	MUX(TOP_MSDC50_0_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),
+	MUX(TOP_MSDC30_1_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),
+	MUX(TOP_MSDC30_2_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
+	/* CLK_CFG_5 */
+	MUX(TOP_AUDIO_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
+	MUX(TOP_AUD_INTBUS_SEL, clk_cfg_5, 8, 2, clk_cfg_update, 21),
+	MUX(TOP_PMICSPI_SEL, clk_cfg_5, 16, 2, clk_cfg_update, 22),
+	MUX(TOP_PWRAP_ULPOSC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23),
+	/* CLK_CFG_6 */
+	MUX(TOP_ATB_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24),
+	MUX(TOP_PWRMCU_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),
+	MUX(TOP_DPI0_SEL, clk_cfg_6, 16, 4, clk_cfg_update, 26),
+	MUX(TOP_SCAM_SEL, clk_cfg_6, 24, 1, clk_cfg_update, 27),
+	/* CLK_CFG_7 */
+	MUX(TOP_DISP_PWM_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
+	MUX(TOP_USB_TOP_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
+	MUX(TOP_SSUSB_XHCI_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30),
+	MUX(TOP_SPM_SEL, clk_cfg_7, 24, 1, clk_cfg_update1, 0),
+	/* CLK_CFG_8 */
+	MUX(TOP_I2C_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1),
+	MUX(TOP_SCP_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2),
+	MUX(TOP_SENINF_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3),
+	MUX(TOP_DXCC_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4),
+	/* CLK_CFG_9 */
+	MUX(TOP_AUD_ENGEN1_SEL, clk_cfg_9, 0, 2, clk_cfg_update1, 5),
+	MUX(TOP_AUD_ENGEN2_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 6),
+	MUX(TOP_AES_UFSFDE_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7),
+	MUX(TOP_UFS_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8),
+	/* CLK_CFG_10 */
+	MUX(TOP_AUD_1_SEL, clk_cfg_10, 0, 1, clk_cfg_update1, 9),
+	MUX(TOP_AUD_2_SEL, clk_cfg_10, 8, 1, clk_cfg_update1, 10),
+};
+
+struct mux_sel {
+	enum mux_id id;
+	u32 sel;
+};
+
+static const struct mux_sel mux_sels[] = {
+	/* CLK_CFG_0 */
+	{ .id = TOP_AXI_SEL, .sel = 2 },		/* 2: mainpll_d7 */
+	{ .id = TOP_MM_SEL, .sel = 1 },			/* 1: mmpll_d7 */
+	{ .id = TOP_IMG_SEL, .sel = 1 },		/* 1: mmpll_d6 */
+	{ .id = TOP_CAM_SEL, .sel = 1 },		/* 1: mainpll_d2 */
+	/* CLK_CFG_1 */
+	{ .id = TOP_DSP_SEL, .sel = 1 },		/* 1: mmpll_d6 */
+	{ .id = TOP_DSP1_SEL, .sel = 1 },		/* 1: mmpll_d6 */
+	{ .id = TOP_DSP2_SEL, .sel = 1 },		/* 1: mmpll_d6 */
+	{ .id = TOP_IPU_IF_SEL, .sel = 1 },		/* 1: mmpll_d6 */
+	/* CLK_CFG_2 */
+	{ .id = TOP_MFG_SEL, .sel = 1 },		/* 1: mfgpll_ck */
+	{ .id = TOP_MFG_52M_SEL, .sel = 3 },		/* 3: univpll_d3_d8 */
+	{ .id = TOP_CAMTG_SEL, .sel = 1 },		/* 1: univ_192m_d8 */
+	{ .id = TOP_CAMTG2_SEL, .sel = 1 },		/* 1: univ_192m_d8 */
+	/* CLK_CFG_3 */
+	{ .id = TOP_CAMTG3_SEL, .sel = 1 },		/* 1: univ_192m_d8 */
+	{ .id = TOP_CAMTG4_SEL, .sel = 1 },		/* 1: univ_192m_d8 */
+	{ .id = TOP_UART_SEL, .sel = 0 },		/* 0: clk26m */
+	{ .id = TOP_SPI_SEL, .sel = 1 },		/* 1: mainpll_d5_d2 */
+	/* CLK_CFG_4 */
+	{ .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 },	/* 1: mainpll_d2_d2 */
+	{ .id = TOP_MSDC50_0_SEL, .sel = 1 },		/* 1: msdcpll_ck */
+	{ .id = TOP_MSDC30_1_SEL, .sel = 4 },		/* 4: msdcpll_d2 */
+	{ .id = TOP_MSDC30_2_SEL, .sel = 1 },		/* 1: univpll_d3_d2 */
+	/* CLK_CFG_5 */
+	{ .id = TOP_AUDIO_SEL, .sel = 0 },		/* 0: clk26m */
+	{ .id = TOP_AUD_INTBUS_SEL, .sel = 1 },		/* 1: mainpll_d2_d4 */
+	{ .id = TOP_PMICSPI_SEL, .sel = 0 },		/* 0: clk26m */
+	{ .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 },	/* 0: clk26m */
+	/* CLK_CFG_6 */
+	{ .id = TOP_ATB_SEL, .sel = 1 },		/* 1: mainpll_d2_d2 */
+	{ .id = TOP_PWRMCU_SEL, .sel = 2 },		/* 2: mainpll_d2_d2 */
+	{ .id = TOP_DPI0_SEL, .sel = 1 },		/* 1: tvdpll_d2 */
+	{ .id = TOP_SCAM_SEL, .sel = 1 },		/* 1: mainpll_d5_d2 */
+	/* CLK_CFG_7 */
+	{ .id = TOP_DISP_PWM_SEL, .sel = 0 },		/* 0: clk26m */
+	{ .id = TOP_USB_TOP_SEL, .sel = 3 },		/* 3: univpll_d5_d2 */
+	{ .id = TOP_SSUSB_XHCI_SEL, .sel = 3 },		/* 3: univpll_d5_d2 */
+	{ .id = TOP_SPM_SEL, .sel = 1 },		/* 1: mainpll_d2_d8 */
+	/* CLK_CFG_8 */
+	{ .id = TOP_I2C_SEL, .sel = 2 },		/* 2: univpll_d5_d2 */
+	{ .id = TOP_SCP_SEL, .sel = 1 },		/* 1: univpll_d2_d8 */
+	{ .id = TOP_SENINF_SEL, .sel = 1 },		/* 1: univpll_d2_d2 */
+	{ .id = TOP_DXCC_SEL, .sel = 1 },		/* 1: mainpll_d2_d2 */
+	/* CLK_CFG_9 */
+	{ .id = TOP_AUD_ENGEN1_SEL, .sel = 3 },		/* 3: apll1_d8 */
+	{ .id = TOP_AUD_ENGEN2_SEL, .sel = 3 },		/* 3: apll2_d8 */
+	{ .id = TOP_AES_UFSFDE_SEL, .sel = 3 },		/* 3: mainpll_d3 */
+	{ .id = TOP_UFS_SEL, .sel = 1 },		/* 1: mainpll_d2_d4 */
+	/* CLK_CFG_10 */
+	{ .id = TOP_AUD_1_SEL, .sel = 1 },		/* 1: apll1_ck */
+	{ .id = TOP_AUD_2_SEL, .sel = 1 },		/* 1: apll2_ck */
+};
+
+#define MMPLL_RSTB_SHIFT	(23)
+
+enum pll_id {
+	APMIXED_ARMPLL_LL,
+	APMIXED_ARMPLL_L,
+	APMIXED_CCIPLL,
+	APMIXED_MAINPLL,
+	APMIXED_UNIVPLL,
+	APMIXED_MSDCPLL,
+	APMIXED_MMPLL,
+	APMIXED_MFGPLL,
+	APMIXED_TVDPLL,
+	APMIXED_APLL1,
+	APMIXED_APLL2,
+	APMIXED_NR_PLL
+};
+
+const u32 pll_div_rate[] = {
+	3800UL * MHz,
+	1248 * MHz,
+	624 * MHz,
+	384 * MHz,
+	200 * MHz,
+	0,
+};
+
+static const struct pll plls[] = {
+	PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_pwr_con0,
+		PLL_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_ARMPLL_L, armpll_l_con0, armpll_l_pwr_con0,
+		PLL_RSTB_SHIFT, 22, armpll_l_con1, 24, armpll_l_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_pwr_con0,
+		PLL_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0,
+		PLL_RSTB_SHIFT, 22, mainpll_con1, 24, mainpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0,
+		PLL_RSTB_SHIFT, 22, univpll_con1, 24, univpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0,
+		NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0,
+		MMPLL_RSTB_SHIFT, 22, mmpll_con1, 24, mmpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_pwr_con0,
+		NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0,
+		NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0,
+		NO_RSTB_SHIFT, 32, apll1_con0, 1, apll1_con1, 0,
+		pll_div_rate),
+	PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0,
+		NO_RSTB_SHIFT, 32, apll2_con0, 1, apll2_con1, 0,
+		pll_div_rate),
+};
+
+struct rate {
+	enum pll_id id;
+	u32 rate;
+};
+
+static const struct rate rates[] = {
+	{ .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
+	{ .id = APMIXED_ARMPLL_L, .rate = ARMPLL_L_HZ },
+	{ .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
+	{ .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
+	{ .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
+	{ .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
+	{ .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
+	{ .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
+	{ .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
+	{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
+	{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
+};
+
+void pll_set_pcw_change(const struct pll *pll)
+{
+	setbits_le32(pll->div_reg, PLL_PCW_CHG);
+}
+
+void mt_pll_init(void)
+{
+	int i;
+
+	/* enable univpll & mainpll div */
+	setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
+
+	/* enable clock square1 low-pass filter */
+	setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
+
+	/* xPLL PWR ON */
+	for (i = 0; i < APMIXED_NR_PLL; i++)
+		setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
+
+	udelay(PLL_PWR_ON_DELAY);
+
+	/* xPLL ISO Disable */
+	for (i = 0; i < APMIXED_NR_PLL; i++)
+		clrbits_le32(plls[i].pwr_reg, PLL_ISO);
+
+	udelay(PLL_ISO_DELAY);
+
+	/* xPLL Frequency Set */
+	for (i = 0; i < ARRAY_SIZE(rates); i++)
+		pll_set_rate(&plls[rates[i].id], rates[i].rate);
+
+	/* AUDPLL Tuner Frequency Set */
+	write32(&mtk_apmixed->apll1_con2,
+		read32(&mtk_apmixed->apll1_con1) + 1);
+	write32(&mtk_apmixed->apll2_con2,
+		read32(&mtk_apmixed->apll2_con1) + 1);
+
+	/* xPLL Frequency Enable */
+	for (i = 0; i < APMIXED_NR_PLL; i++)
+		setbits_le32(plls[i].reg, PLL_EN);
+
+	/* wait for PLL stable */
+	udelay(PLL_EN_DELAY);
+
+	/* xPLL DIV RSTB */
+	for (i = 0; i < APMIXED_NR_PLL; i++) {
+		if (plls[i].rstb_shift != NO_RSTB_SHIFT)
+			setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
+	}
+
+	/* MCUCFG CLKMUX */
+	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
+
+	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
+		MUX_SRC_ARMPLL);
+	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
+		MUX_SRC_ARMPLL);
+	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
+		MUX_SRC_ARMPLL);
+
+	/* enable infrasys DCM */
+	setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
+
+	/*
+	 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
+	 */
+	for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
+		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+
+	/* enable [14] dramc_pll104m_ck */
+	setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+}