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armv7: import updated cache/MMU stuff from coreboot 

This imports the cache/MMU code from coreboot as of 1877cee.

Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/48288
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-03-29 13:24:29 -07:00 committed by Stefan Reinauer
parent 7905f9254e
commit 6119bea233
2 changed files with 54 additions and 14 deletions
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43
payloads/libpayload/arch/armv7/cache.c
View File

@ -31,7 +31,7 @@
* Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
*/
#include <inttypes.h>
#include <stdint.h>
#include <arch/cache.h>
@ -149,14 +149,39 @@ static void dcache_op_set_way(enum dcache_op op)
isb();
}
static void dcache_foreach(enum dcache_op op)
{
uint32_t clidr;
int level;
clidr = read_clidr();
for (level = 0; level < 7; level++) {
unsigned int ctype = (clidr >> (level * 3)) & 0x7;
uint32_t csselr;
switch(ctype) {
case 0x2:
case 0x3:
case 0x4:
csselr = level << 1;
write_csselr(csselr);
dcache_op_set_way(op);
break;
default:
/* no cache, icache only, or reserved */
break;
}
}
}
void dcache_clean_invalidate_all(void)
{
dcache_op_set_way(OP_DCCISW);
dcache_foreach(OP_DCCISW);
}
void dcache_invalidate_all(void)
{
dcache_op_set_way(OP_DCISW);
dcache_foreach(OP_DCISW);
}
static unsigned int line_bytes(void)
@ -212,15 +237,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
void dcache_mmu_disable(void)
{
uint32_t sctlr, csselr;
/* ensure L1 data/unified cache is selected */
csselr = read_csselr();
csselr &= ~0xf;
write_csselr(csselr);
uint32_t sctlr;
dcache_clean_invalidate_all();
sctlr = read_sctlr();
sctlr &= ~(SCTLR_C | SCTLR_M);
write_sctlr(sctlr);
@ -264,6 +283,8 @@ void armv7_invalidate_caches(void)
case 0x2:
case 0x4:
/* dcache only or unified cache */
csselr = level << 1;
write_csselr(csselr);
dcache_invalidate_all();
break;
case 0x3:
@ -272,7 +293,7 @@ void armv7_invalidate_caches(void)
write_csselr(csselr);
icache_invalidate_all();
csselr = level < 1;
csselr = level << 1;
write_csselr(csselr);
dcache_invalidate_all();
break;

25
payloads/libpayload/include/armv7/arch/cache.h
View File

@ -219,10 +219,29 @@ static inline void write_csselr(uint32_t val)
isb(); /* ISB to sync the change to CCSIDR */
}
/* read system control register (SCTLR) */
static inline unsigned int read_sctlr(void)
/* read L2 control register (L2CTLR) */
static inline uint32_t read_l2ctlr(void)
{
unsigned int val;
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
return val;
}
/* write L2 control register (L2CTLR) */
static inline void write_l2ctlr(uint32_t val)
{
/*
* Note: L2CTLR can only be written when the L2 memory system
* is idle, ie before the MMU is enabled.
*/
asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
isb();
}
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{
uint32_t val;
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
return val;
}