drivers/intel/gma/acpi: Add Kconfigs for backlight registers

Instead of adding more versions of the `*pch.asl`, unify the existing
ones and allow to override the register locations via Kconfig. The
current defaults should work for Skylake and some newer platforms.

TEST=Booted ThinkPad X201s, backlight control still works.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>

src/drivers/intel/gma/Kconfig

@@ -29,6 +29,22 @@ config INTEL_GMA_ACPI
 	bool
 	default n
 
+config INTEL_GMA_BCLV_OFFSET
+	hex
+	default 0xc8254
+
+config INTEL_GMA_BCLV_WIDTH
+	int
+	default 16
+
+config INTEL_GMA_BCLM_OFFSET
+	hex
+	default 0xc8256
+
+config INTEL_GMA_BCLM_WIDTH
+	int
+	default 16
+
 config INTEL_GMA_SSC_ALTERNATE_REF
 	bool
 	default n

src/drivers/intel/gma/acpi/gma.asl

@@ -19,9 +19,10 @@ Device (GFX0)
 	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
 	Field (GFRG, DWordAcc, NoLock, Preserve)
 	{
-		Offset (0x61254),
-		BCLV, 16,
-		BCLM, 16,
+		Offset (CONFIG_INTEL_GMA_BCLV_OFFSET),
+		BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH,
+		Offset (CONFIG_INTEL_GMA_BCLM_OFFSET),
+		BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH
 	}
 
 #include "configure_brightness_levels.asl"

src/drivers/intel/gma/acpi/pch.asl

@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64,
-		Offset (0xe4),
-		ASLE, 32,
-		Offset (0xfc),
-		ASLS, 32,
-	}
-
-	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-		BCLV, 16,
-		Offset (0xc8256),
-		BCLM, 16
-	}
-
-#include "configure_brightness_levels.asl"
-#include "common.asl"
-}

src/northbridge/intel/gm45/Kconfig

@@ -46,4 +46,10 @@ config SMM_RESERVED_SIZE
 	hex
 	default 0x100000
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0x61254
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0x61256
+
 endif

src/northbridge/intel/gm45/acpi/gm45.asl

@@ -75,4 +75,4 @@ Device (PDRC)
 #include "peg.asl"
 
 // Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/non-pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>

src/northbridge/intel/haswell/Kconfig

@@ -107,4 +107,7 @@ config RO_REGION_ONLY
 	depends on VBOOT
 	default "mrc.bin"
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif

src/northbridge/intel/haswell/acpi/haswell.asl

@@ -48,4 +48,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>

src/northbridge/intel/ironlake/Kconfig

@@ -61,4 +61,7 @@ config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif

src/northbridge/intel/ironlake/acpi/ironlake.asl

@@ -51,4 +51,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>

src/northbridge/intel/sandybridge/Kconfig

@@ -121,4 +121,7 @@ config MRC_FILE
 
 endif # !USE_NATIVE_RAMINIT
 
+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif

src/northbridge/intel/sandybridge/acpi/sandybridge.asl

@@ -55,4 +55,4 @@ Device (PDRC)
 }
 
 // Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>

src/northbridge/intel/x4x/acpi/x4x.asl

@@ -45,4 +45,4 @@ Device (PDRC)
 #include "peg.asl"
 
 // Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/non-pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>