- fix irq routing for epia-mii cardbus slot. (signed off by Nick Barker)
- some minor cleanups git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
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9cf0050d68
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613cb6171f
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@ -132,6 +132,13 @@ dir /pc80
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config chip.h
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config chip.h
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chip northbridge/via/vt8623
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chip northbridge/via/vt8623
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device apic_cluster 0 on
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chip cpu/via/model_centaur
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci_domain 0 on
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chip southbridge/via/vt8235
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chip southbridge/via/vt8235
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@ -180,10 +187,4 @@ chip northbridge/via/vt8623
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device pci 0a.1 on end
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device pci 0a.1 on end
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end
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end
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end
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end
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device apic_cluster 0 on
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chip cpu/via/model_centaur
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device apic 0 on end
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end
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end
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end
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end
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@ -21,6 +21,7 @@ uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_COMPRESSED_ROM_STREAM
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uses PAYLOAD_SIZE
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _ROMBASE
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uses _RAMBASE
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uses _RAMBASE
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@ -32,17 +32,11 @@ void udelay(int usecs)
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#include "southbridge/via/vt8235/vt8235_early_smbus.c"
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#include "southbridge/via/vt8235/vt8235_early_smbus.c"
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#include "southbridge/via/vt8235/vt8235_early_serial.c"
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#include "southbridge/via/vt8235/vt8235_early_serial.c"
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static void memreset_setup(void)
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static void memreset_setup(void)
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{
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{
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}
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}
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/*
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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{
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unsigned char c;
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unsigned char c;
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@ -50,12 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return c;
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return c;
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}
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}
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#include "northbridge/via/vt8623/raminit.c"
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#include "northbridge/via/vt8623/raminit.c"
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/*
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#include "sdram/generic_sdram.c"
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*/
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static void enable_mainboard_devices(void)
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static void enable_mainboard_devices(void)
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{
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{
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@ -71,12 +60,11 @@ static void enable_mainboard_devices(void)
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pci_write_config8(dev, 0x51, 0x1f);
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pci_write_config8(dev, 0x51, 0x1f);
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#if 0
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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// PCI_WRITE_CONFIG_BYTE
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//
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#endif
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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* to pci!
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@ -132,7 +120,7 @@ static void main(unsigned long bist)
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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report_bist_failure(bist);
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/* init_timer();*/
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// init_timer();
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outb(5, 0x80);
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outb(5, 0x80);
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@ -170,5 +158,7 @@ static void main(unsigned long bist)
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early_mtrr_init();
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early_mtrr_init();
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}
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}
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//dump_pci_devices();
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print_spew("Leaving auto.c:main()\r\n");
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print_spew("Leaving auto.c:main()\r\n");
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}
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}
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@ -205,10 +205,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
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/* PCI Routing Table */
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/* PCI Routing Table */
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Name (_PRT, Package () {
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Name (_PRT, Package () {
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Package () {0x000AFFFF, 0x00, LNKD, 0x00}, // Cardbus Link D
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/* Epia-MII 6000e cardbus: */
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Package () {0x000AFFFF, 0x01, LNKA, 0x00}, // Cardbus Link A
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Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A
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Package () {0x000AFFFF, 0x02, LNKB, 0x00}, // Cardbus Link B
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Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B
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Package () {0x000AFFFF, 0x03, LNKC, 0x00}, // Cardbus Link C
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Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C
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Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
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Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
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Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
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Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
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Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
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@ -1,11 +1,11 @@
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/*
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/*
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*
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*
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* Intel ACPI Component Architecture
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* Intel ACPI Component Architecture
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* ASL Optimizing Compiler / AML Disassembler version 20040715 [Aug 16 2004]
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* ASL Optimizing Compiler version 20060127 [Apr 23 2006]
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* Copyright (C) 2000 - 2004 Intel Corporation
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* Copyright (C) 2000 - 2006 Intel Corporation
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* Supports ACPI Specification Revision 2.0c
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* Supports ACPI Specification Revision 3.0a
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*
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*
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* Compilation of "dsdt.asl" - Thu Oct 27 09:25:57 2005
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* Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006
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*
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*
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* C source code output
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* C source code output
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*
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*
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@ -13,10 +13,10 @@
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unsigned char AmlCode[] =
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unsigned char AmlCode[] =
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{
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{
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0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */
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0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */
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0x01,0x11,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
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0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */
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0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */
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0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */
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0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
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0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
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0x15,0x07,0x04,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "... .._P" */
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0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */
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0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */
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0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */
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0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */
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0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */
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0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */
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0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */
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0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08, /* 00000210 ".._BBN.." */
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0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08, /* 00000210 ".._BBN.." */
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0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20, /* 00000218 "_PRT.C. " */
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0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20, /* 00000218 "_PRT.C. " */
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0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00, /* 00000220 "........" */
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0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00, /* 00000220 "........" */
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0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000228 ".LNKD..." */
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0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000228 ".LNKA..." */
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0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C, /* 00000230 ".......L" */
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0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C, /* 00000230 ".......L" */
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0x4E,0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKA....." */
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0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKB....." */
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0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E, /* 00000240 "......LN" */
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0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E, /* 00000240 "......LN" */
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0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KB......" */
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0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KC......" */
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0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000250 ".....LNK" */
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0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000250 ".....LNK" */
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0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "C......." */
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0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "D......." */
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0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00, /* 00000260 "...LNKB." */
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0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00, /* 00000260 "...LNKB." */
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0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00, /* 00000268 "........" */
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0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00, /* 00000268 "........" */
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0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00000270 ".LNKC..." */
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0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00000270 ".LNKC..." */
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