Move gpio.h to gpio.c on sandy and ivy.

Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13657
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/link/Makefile.inc

@@ -42,3 +42,4 @@ $(SPD_BIN): $(SPD_DEPS)
 cbfs-files-y += spd.bin
 spd.bin-file := $(SPD_BIN)
 spd.bin-type := spd
+romstage-y += gpio.c

src/mainboard/google/link/romstage.c

@@ -29,13 +29,12 @@
 #include <console/console.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/bd82x6x/gpio.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 #include "ec/google/chromeec/ec.h"
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include "gpio.h"
 #include <tpm.h>
 #include <cbfs.h>
 

src/mainboard/google/parrot/Makefile.inc

@@ -17,3 +17,4 @@ ramstage-y += ec.c
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+romstage-y += gpio.c

src/mainboard/google/parrot/romstage.c

@@ -29,11 +29,9 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include "gpio.h"
 #include <cbfs.h>
 #include <tpm.h>
 #include "ec/compal/ene932/ec.h"

src/mainboard/google/stout/Makefile.inc

@@ -22,3 +22,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
 
 SRC_ROOT = $(src)/mainboard/google/stout
+romstage-y += gpio.c

src/mainboard/google/stout/romstage.c

@@ -29,11 +29,9 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include "gpio.h"
 #include <bootmode.h>
 #include <tpm.h>
 #include <cbfs.h>

src/mainboard/intel/emeraldlake2/Makefile.inc

@@ -15,3 +15,4 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+romstage-y += gpio.c

src/mainboard/intel/emeraldlake2/romstage.c

@@ -30,12 +30,10 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <tpm.h>
-#include "gpio.h"
 
 #define SIO_PORT 0x164e
 

src/mainboard/kontron/ktqm77/Makefile.inc

@@ -0,0 +1 @@
+romstage-y += gpio.c

src/mainboard/kontron/ktqm77/romstage.c

@@ -29,11 +29,9 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
-#include "gpio.h"
 
 void pch_enable_lpc(void)
 {

src/mainboard/samsung/lumpy/Makefile.inc

@@ -27,3 +27,4 @@ $(SPD_BIN):
 cbfs-files-y += spd.bin
 spd.bin-file := $(SPD_BIN)
 spd.bin-type := spd
+romstage-y += gpio.c

src/mainboard/samsung/lumpy/romstage.c

@@ -32,12 +32,10 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include "option_table.h"
-#include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif

src/mainboard/samsung/stumpy/Makefile.inc

@@ -15,3 +15,4 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
+romstage-y += gpio.c

src/mainboard/samsung/stumpy/romstage.c

@@ -32,12 +32,10 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <tpm.h>
-#include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif