amd/stoneyridge: Make gnvs ASL whitespace consistent
The globalnvs.asl file had become mixed with tabs and spaces to align columns. Use all tabs to align the comments. BUG=b:BUG=b:77602074 Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -28,19 +28,19 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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{
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/* Miscellaneous */
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/* Miscellaneous */
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Offset (0x00),
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Offset (0x00),
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PCNT, 8, // 0x00 - Processor Count
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x01 - Max PPC State
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x02 - LID State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x03 - AC Power State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x04 - Enable DPTF
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
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CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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SCDP, 8, // 0x29 - SD_CD GPIO portid
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SCDP, 8, // 0x29 - SD_CD GPIO portid
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SCDO, 8, // 0x2A - GPIO pad offset relative to the community
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SCDO, 8, // 0x2A - GPIO pad offset relative to the community
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TMPS, 8, // 0x2B - Temperature Sensor ID
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TMPS, 8, // 0x2B - Temperature Sensor ID
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TLVL, 8, // 0x2C - Throttle Level Limit
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TLVL, 8, // 0x2C - Throttle Level Limit
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FLVL, 8, // 0x2D - Current FAN Level
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FLVL, 8, // 0x2D - Current FAN Level
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