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soc/intel/quark: Identify the console UART 

Pass the UART identifier to CorebootPayloadPkg

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing is successful when CorebootPayloadPkg is able to properly
   initialize the serial port without using built-in values.

Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14610
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-05-04 12:50:51 -07:00 committed by Leroy P Leahy
parent f92a98c56e
commit 614ef40815
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/quark/Kconfig
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@ -60,6 +60,13 @@ config TTYS0_LCS
depends on ENABLE_BUILTIN_HSUART1
default 3
# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12
# Valid bit, PCI UART in use: 1 << 31
config UART_PCI_ADDR
hex
depends on ENABLE_BUILTIN_HSUART1
default 0x800a5000
#####
# Debug support
# The following options provide debug support for the Quark coreboot