diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index c5ca8b40d9..c6ba09f282 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -25,13 +25,13 @@ #define OUT #ifndef Int16FromChar -#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#define Int16FromChar(a, b) ((a) << 0 | (b) << 8) #endif #ifndef Int32FromChar -#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#define Int32FromChar(a, b, c, d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #endif -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IMAGE_SIGNATURE Int32FromChar('$', 'A', 'M', 'D') typedef unsigned int AGESA_STATUS; diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index 269dc7f58a..694fffd973 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -5,9 +5,9 @@ #include -#pragma pack (push, 1) +#pragma pack(push, 1) -#define IMAGE_ALIGN 32*1024 +#define IMAGE_ALIGN 32 * 1024 #define NUM_IMAGE_LOCATION 32 //Entry Point Call @@ -104,7 +104,7 @@ typedef struct _CIMFILEHEADER #ifndef BIT23 #define BIT23 (1 << 23) #endif -#ifndef BIT24 +#ifndef BIT24 #define BIT24 (1 << 24) #endif #ifndef BIT25 @@ -129,7 +129,7 @@ typedef struct _CIMFILEHEADER #define BIT31 (1 << 31) #endif -#pragma pack (pop) +#pragma pack(pop) typedef enum { diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 9ac67f3dff..636e5a8eec 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -55,7 +55,7 @@ static void enable_spi_fast_mode(void) // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; u32 save = pci_s_read_config32(dev, 0xa0); - pci_s_write_config32(dev, 0xa0, (u32) spi_base | 2); + pci_s_write_config32(dev, 0xa0, (u32)spi_base | 2); // early enable of SPI 33 MHz fast mode read dword = spi_base[3]; diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index d11fbcfc66..9b763a5877 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -71,16 +71,16 @@ void init_sb800_MANUAL_fans(struct device *dev); #define FREQ_11HZ 0xFF /* IMC Fan Control Definitions */ -#define IMC_MODE1_FAN_ENABLED ( 1 << 0 ) -#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 ) -#define IMC_MODE1_FAN_LINEAR_MODE ( 1 << 4 ) +#define IMC_MODE1_FAN_ENABLED (1 << 0) +#define IMC_MODE1_FAN_IMC_CONTROLLED (1 << 2) +#define IMC_MODE1_FAN_LINEAR_MODE (1 << 4) #define IMC_MODE1_FAN_STEP_MODE 0 /* ~( 1 << 4 ) */ #define IMC_MODE1_NO_FANOUT 0 /* ~( 7 << 5 ) */ -#define IMC_MODE1_FANOUT0 ( 1 << 5 ) -#define IMC_MODE1_FANOUT1 ( 2 << 5 ) -#define IMC_MODE1_FANOUT2 ( 3 << 5 ) -#define IMC_MODE1_FANOUT3 ( 4 << 5 ) -#define IMC_MODE1_FANOUT4 ( 5 << 5 ) +#define IMC_MODE1_FANOUT0 (1 << 5) +#define IMC_MODE1_FANOUT1 (2 << 5) +#define IMC_MODE1_FANOUT2 (3 << 5) +#define IMC_MODE1_FANOUT3 (4 << 5) +#define IMC_MODE1_FANOUT4 (5 << 5) #define IMC_MODE2_TEMPIN_NONE 0 /* ~( 7 << 0) */ #define IMC_MODE2_TEMPIN_0 1 @@ -91,12 +91,12 @@ void init_sb800_MANUAL_fans(struct device *dev); #define IMC_MODE2_TEMPIN_SB_TSI 6 #define IMC_MODE2_TEMPIN_OTHER 7 #define IMC_MODE2_FANIN_NONE 0 /* ~ (7 << 3) */ -#define IMC_MODE2_FANIN0 ( 1 << 3 ) -#define IMC_MODE2_FANIN1 ( 2 << 3 ) -#define IMC_MODE2_FANIN2 ( 3 << 3 ) -#define IMC_MODE2_FANIN3 ( 4 << 3 ) -#define IMC_MODE2_FANIN4 ( 5 << 3 ) -#define IMC_MODE2_TEMP_AVERAGING_ENABLED ( 1 << 6 ) +#define IMC_MODE2_FANIN0 (1 << 3) +#define IMC_MODE2_FANIN1 (2 << 3) +#define IMC_MODE2_FANIN2 (3 << 3) +#define IMC_MODE2_FANIN3 (4 << 3) +#define IMC_MODE2_FANIN4 (5 << 3) +#define IMC_MODE2_TEMP_AVERAGING_ENABLED (1 << 6) #define IMC_MODE2_TEMP_AVERAGING_DISABLED 0 /* ~( 1 << 6 ) */ #define IMC_TEMP_SENSOR_ON_SMBUS_0 0 @@ -113,17 +113,17 @@ void init_sb800_MANUAL_fans(struct device *dev); #define IMC_TEMPIN_TUNING_DEFAULT_MODE 0 #define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO 1 #define IMC_TEMPIN_TUNING_HIGH_CURRENT 2 -#define IMC_TEMPIN_TUNING_DISABLE_FILTERING ( 1 << 2 ) +#define IMC_TEMPIN_TUNING_DISABLE_FILTERING (1 << 2) /* IMCFUNSupportBitMap - Zone enable values */ #define IMC_ENABLE_ZONE0 0x111 #define IMC_ENABLE_ZONE1 0x222 #define IMC_ENABLE_ZONE2 0x333 #define IMC_ENABLE_ZONE3 0x444 -#define IMC_ENABLE_TEMPIN0 ( 1 << 12 ) -#define IMC_ENABLE_TEMPIN1 ( 1 << 13 ) -#define IMC_ENABLE_TEMPIN2 ( 1 << 14 ) -#define IMC_ENABLE_TEMPIN3 ( 1 << 15 ) +#define IMC_ENABLE_TEMPIN0 (1 << 12) +#define IMC_ENABLE_TEMPIN1 (1 << 13) +#define IMC_ENABLE_TEMPIN2 (1 << 14) +#define IMC_ENABLE_TEMPIN3 (1 << 15) /* Array size settings */ #define IMC_FAN_THRESHOLD_COUNT 9 diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index 8bd168ef14..f61db5a6bf 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -13,9 +13,9 @@ #define SB_GPIO_REG28 28 /* FCH GPIO access helpers */ -#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) -#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) -#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) +#define FCH_IOMUX(gpio_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + IOMUX_BASE + (gpio_nr))) +#define FCH_PMIO(reg_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + PMIO_BASE + (reg_nr))) +#define FCH_GPIO(gpio_nr) (*(volatile u8 *)((uintptr_t)ACPI_MMIO_BASE + GPIO_BASE + (gpio_nr))) static inline u8 fch_gpio_state(unsigned int gpio_nr) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index da2c5ab88a..88e426a1c5 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -88,7 +88,7 @@ static void ahci_raid_init(struct device *dev) caps = read32(bar5 + HOST_CAP); caps = (caps & 0x1F) + 1; - ports= read32(bar5 + HOST_PORTS_IMPL); + ports = read32(bar5 + HOST_PORTS_IMPL); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); /* make sure ahci is enabled */ @@ -382,7 +382,7 @@ static void sb800_enable(struct device *dev) { struct device *device; for (device = dev; device; device = device->sibling) { - if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15,0)) break; + if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break; sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; } diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index b04c3e2918..6c8f0e426c 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -8,10 +8,10 @@ #include #define HT_INIT_CONTROL 0x6c -#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_BIOSR_Detect (1 << 5) #define DEV_CDB 0x18 -#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn))) +#define NODE_PCI(x, fn) (((DEV_CDB + x) < 32) ? (PCI_DEV(0, (DEV_CDB + x), fn)) : (PCI_DEV((0 - 1), (DEV_CDB + x - 32), fn))) void cf9_reset_prepare(void) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 38439d0d93..792a4a1d7e 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -29,7 +29,7 @@ static void execute_command(void) write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1); while ((read8((void *)(spibar + 2)) & 1) && - (read8((void *)(spibar+3)) & 0x80)); + (read8((void *)(spibar + 3)) & 0x80)); } void spi_init(void) @@ -98,9 +98,9 @@ static void ImcSleep(void) u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB4; /* request ownership flag */ - WriteECmsg (MSG_REG0, AccWidthUint8, ®0_val); - WriteECmsg (MSG_REG1, AccWidthUint8, ®1_val); - WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); + WriteECmsg(MSG_REG0, AccWidthUint8, ®0_val); + WriteECmsg(MSG_REG1, AccWidthUint8, ®1_val); + WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); WaitForEcLDN9MailboxCmdAck(); } @@ -111,9 +111,9 @@ static void ImcWakeup(void) u8 reg0_val = 0; /* clear response register */ u8 reg1_val = 0xB5; /* release ownership flag */ - WriteECmsg (MSG_REG0, AccWidthUint8, ®0_val); - WriteECmsg (MSG_REG1, AccWidthUint8, ®1_val); - WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); + WriteECmsg(MSG_REG0, AccWidthUint8, ®0_val); + WriteECmsg(MSG_REG1, AccWidthUint8, ®1_val); + WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); WaitForEcLDN9MailboxCmdAck(); }