Initial revision.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Steven J. Magnani
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/*
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* $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
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*
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* sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
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*
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*
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* Copyright (C) 2005 Digital Design Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* $Log: sdram_mode.h,v $
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* Revision 1.1 2005/07/11 16:03:54 smagnani
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* Initial revision.
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*
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*
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*/
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#ifndef __SDRAMMODE_H_DEFINED
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#define __SDRAMMODE_H_DEFINED
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// SDRAM Mode Register definitions, per JESD79D
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// These are transmitted via A0-A13
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// Burst length
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#define SDRAM_BURST_2 (1<<0)
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#define SDRAM_BURST_4 (2<<0)
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#define SDRAM_BURST_8 (3<<0)
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#define SDRAM_BURST_SEQUENTIAL (0<<3)
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#define SDRAM_BURST_INTERLEAVED (1<<3)
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#define SDRAM_CAS_2_0 (2<<4)
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#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */
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#define SDRAM_CAS_1_5 (5<<4) /* Optional */
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#define SDRAM_CAS_2_5 (6<<4)
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#define SDRAM_CAS_MASK (7<<4)
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#define SDRAM_MODE_NORMAL (0 << 7)
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#define SDRAM_MODE_TEST (1 << 7)
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#define SDRAM_MODE_DLL_RESET (2 << 7)
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// Extended Mode Register
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#define SDRAM_EXTMODE_DLL_ENABLE (0 << 0)
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#define SDRAM_EXTMODE_DLL_DISABLE (1 << 0)
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#define SDRAM_EXTMODE_DRIVE_NORMAL (0 << 1)
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#define SDRAM_EXTMODE_DRIVE_WEAK (1 << 1) /* Optional */
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#endif // __SDRAMMODE_H_DEFINED
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/*
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* $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
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*
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* spd.h: Definitions for Serial Presence Detect (SPD) data
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* stored on SDRAM modules
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*
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* Copyright (C) 2005 Digital Design Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* $Log: spd.h,v $
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* Revision 1.1 2005/07/11 16:03:54 smagnani
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* Initial revision.
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*
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*
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*/
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#ifndef __SPD_H_DEFINED
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#define __SPD_H_DEFINED
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// Byte numbers
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#define SPD_MEMORY_TYPE 2
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#define SPD_NUM_ROWS 3
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#define SPD_NUM_COLUMNS 4
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#define SPD_NUM_DIMM_BANKS 5
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#define SPD_MODULE_DATA_WIDTH_LSB 6
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#define SPD_MODULE_DATA_WIDTH_MSB 7
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#define SPD_MODULE_VOLTAGE 8
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#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9
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#define SPD_DIMM_CONFIG_TYPE 11
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#define SPD_REFRESH 12
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#define SPD_PRIMARY_DRAM_WIDTH 13
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#define SPD_SUPPORTED_BURST_LENGTHS 16
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#define SPD_NUM_BANKS_PER_DRAM 17
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#define SPD_ACCEPTABLE_CAS_LATENCIES 18
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#define SPD_MODULE_ATTRIBUTES 21
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#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05 23
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#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10 25
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#define SPD_MIN_ROW_PRECHARGE_TIME 27
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#define SPD_MIN_RAS_TO_CAS_DELAY 29
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#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30
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#define SPD_ADDRESS_CMD_HOLD 33
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// SPD_MEMORY_TYPE values
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#define MEMORY_TYPE_SDRAM_DDR 7
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// SPD_MODULE_VOLTAGE values
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#define SPD_VOLTAGE_SSTL2 4
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// SPD_DIMM_CONFIG_TYPE values
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#define ERROR_SCHEME_NONE 0
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#define ERROR_SCHEME_PARITY 1
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#define ERROR_SCHEME_ECC 2
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// SPD_ACCEPTABLE_CAS_LATENCIES values
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#define SPD_CAS_LATENCY_1_0 0x01
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#define SPD_CAS_LATENCY_1_5 0x02
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#define SPD_CAS_LATENCY_2_0 0x04
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#define SPD_CAS_LATENCY_2_5 0x08
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#define SPD_CAS_LATENCY_3_0 0x10
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#define SPD_CAS_LATENCY_3_5 0x20
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#define SPD_CAS_LATENCY_4_0 0x40
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// SPD_SUPPORTED_BURST_LENGTHS values
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#define SPD_BURST_LENGTH_1 1
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#define SPD_BURST_LENGTH_2 2
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#define SPD_BURST_LENGTH_4 4
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#define SPD_BURST_LENGTH_8 8
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#define SPD_BURST_LENGTH_PAGE (1<<7)
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// SPD_MODULE_ATTRIBUTES values
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#define MODULE_BUFFERED 1
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#define MODULE_REGISTERED 2
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#endif // __SPD_H_DEFINED
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