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northbridge/intel/gm45/gma: Minor cleanup 

1.) Removed invalid set of TRANS_STATE_MASK bit
2.) Used i915 register defines to clarify code

Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson 2015-04-06 21:54:56 -05:00 committed by Patrick Georgi
parent f88b93214b
commit 61942de689
1 changed files with 5 additions and 8 deletions
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13
src/northbridge/intel/gm45/gma.c
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@ -134,9 +134,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
outl(physbase + (i << 12) + 1, piobase + 4); outl(physbase + (i << 12) + 1, piobase + 4);
} }
write32(mmio + 0x61100, 0x40008c18); write32(mmio + ADPA, 0x40008c18);
write32(mmio + 0x7041c, 0x0); write32(mmio + 0x7041c, 0x0);
write32(mmio + 0x6020, 0x3); write32(mmio + _DPLL_B_MD, 0x3);
vga_misc_write(0x67); vga_misc_write(0x67);
@ -174,9 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock); : (2 * edid.pixel_clock);
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_textmode_init();
#else
vga_sr_write(1, 1); vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf); vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0); vga_sr_write(0x3, 0x0);
@ -200,6 +198,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + DSPSURF(0), 0); write32(mmio + DSPSURF(0), 0);
for (i = 0; i < 0x100; i++) for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
#else
vga_textmode_init();
#endif #endif
/* Find suitable divisors. */ /* Find suitable divisors. */
@ -391,9 +391,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + 0x000f000c, 0xb01a2050); write32(mmio + 0x000f000c, 0xb01a2050);
mdelay(1); mdelay(1);
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
| TRANS_STATE_MASK
#endif
); );
write32(mmio + LVDS, write32(mmio + LVDS,
LVDS_PORT_ENABLE LVDS_PORT_ENABLE