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In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. 

http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html

It's about time we follow this advice.

Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2011-04-10 04:15:23 +00:00 committed by Stefan Reinauer
parent df6fd566ba
commit 61aee5f4b1
23 changed files with 17 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
View File

@ -64,7 +64,6 @@ ifneq ($(Q),)
endif
endif
CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
HOSTCC = gcc
HOSTCXX = g++
HOSTCFLAGS := -I$(srck) -I$(objk) -g

6
Makefile.inc
View File

@ -50,10 +50,8 @@ subdirs-$(CONFIG_ARCH_X86) += src/pc80
# Add source classes and their build options
classes-y := ramstage romstage driver smm
ramstage-S-ccopts:=-DASSEMBLY
romstage-c-ccopts:=-D__PRE_RAM__
romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__
driver-S-ccopts:=-DASSEMBLY
romstage-S-ccopts:=-D__PRE_RAM__
ramstage-c-deps:=$$(OPTION_TABLE_H)
romstage-c-deps:=$$(OPTION_TABLE_H)
@ -63,7 +61,7 @@ romstage-c-deps:=$$(OPTION_TABLE_H)
define ramstage-objs_asl_template
$(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h
@printf " IASL $$(subst $(top)/,,$$(@))\n"
$(CPP) -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl
mv $$(obj)/$(1).hex $$(basename $$@).c
$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c

2
src/arch/x86/Makefile.bigbootblock.inc
View File

@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@
$(obj)/coreboot: $$(romstage-objs) $(obj)/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"

4
src/arch/x86/Makefile.bootblock.inc
View File

@ -55,7 +55,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/b
$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
@ -105,5 +105,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@

2
src/arch/x86/Makefile.inc
View File

@ -225,7 +225,7 @@ else
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"

2
src/include/cpu/amd/gx2def.h
View File

@ -511,7 +511,7 @@
#define PMLogic_BASE (0x9D00)
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
#if defined(__PRE_RAM__)
void cpuRegInit(void);
void SystemPreInit(void);

2
src/include/cpu/amd/lxdef.h
View File

@ -630,7 +630,7 @@
#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
#define DELAY_LOWER_STATUS_MASK 0x7C0
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
#if defined(__PRE_RAM__)
void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
void SystemPreInit(void);

2
src/include/cpu/amd/mtrr.h
View File

@ -33,7 +33,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
#if !defined(__PRE_RAM__) && !defined(ASSEMBLY)
#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
void amd_setup_mtrrs(void);
#endif

4
src/include/cpu/x86/mtrr.h
View File

@ -36,7 +36,7 @@
#define MTRRfix4K_F0000_MSR 0x26e
#define MTRRfix4K_F8000_MSR 0x26f
#if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
#include <device/device.h>
void enable_fixed_mtrr(void);
void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
@ -69,7 +69,7 @@ void x86_setup_fixed_mtrrs(void);
#endif
#if !defined (ASSEMBLY)
#if !defined (__ASSEMBLER__)
#if defined(CONFIG_XIP_ROM_SIZE)
# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
extern unsigned long AUTO_XIP_ROM_BASE;

4
src/include/fallback.h
View File

@ -1,12 +1,12 @@
#ifndef FALLBACK_H
#define FALLBACK_H
#if !defined(ASSEMBLY) && !defined(__PRE_RAM__)
#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__)
void set_boot_successful(void);
void boot_successful(void);
#endif /* ASSEMBLY */
#endif /* __ASSEMBLER__ */
#define RTC_BOOT_BYTE 48

3
src/mainboard/amd/serengeti_cheetah/ap_romstage.c
View File

@ -1,6 +1,3 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
View File

@ -21,9 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/gigabyte/m57sli/ap_romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

4
src/mainboard/msi/ms7260/ap_romstage.c
View File

@ -19,10 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/nvidia/l1_2pvv/ap_romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/supermicro/h8dme/ap_romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/supermicro/h8dmr/ap_romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

3
src/mainboard/tyan/s2912/ap_romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __PRE_RAM__
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#include <stdint.h>

2
src/southbridge/amd/cs5535/cs5535.h
View File

@ -115,7 +115,7 @@
/* Flash Memory Mask values */
#define FLASH_MEM_4K 0xFFFFF000
#if !defined(ASSEMBLY) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if defined(__PRE_RAM__)
void cs5535_disable_internal_uart(void);
#else

2
src/southbridge/amd/cs5536/cs5536.h
View File

@ -442,7 +442,7 @@
#define FLASH_IO_128B 0x0000FF80
#define FLASH_IO_256B 0x0000FF00
#if !defined(ASSEMBLY) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if defined(__PRE_RAM__)
void cs5536_setup_onchipuart(int uart);
void cs5536_disable_internal_uart(void);

2
src/southbridge/intel/i82371eb/i82371eb.h
View File

@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#if !defined(ASSEMBLY)
#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#if !defined(__ACPI__) /* dsdt include */

2
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -38,7 +38,7 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
#if !defined(ASSEMBLY) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);

1
util/xcompile/xcompile
View File

@ -89,7 +89,6 @@ cat << EOF
# elf${TWIDTH}-${TARCH} toolchain
AS:=${GCCPREFIX}as ${ASFLAGS}
CC:=${GCCPREFIX}gcc ${CFLAGS}
CPP:=${GCCPREFIX}cpp
AR:=${GCCPREFIX}ar
LD:=${GCCPREFIX}ld ${LDFLAGS}
STRIP:=${GCCPREFIX}strip