mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier
Patrick Georgi
parent
98f609aad4
commit
61ba3ac92e
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@ -48,9 +48,9 @@ config MAINBOARD_FAMILY
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string
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default "Google_Slippy"
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config DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAX_CPUS
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int
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@ -14,14 +14,6 @@ chip northbridge/intel/haswell
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# Set backlight PWM value for eDP
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4)
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register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2)
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register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7)
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5)
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6)
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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device lapic 0 on end
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@ -79,9 +71,6 @@ chip northbridge/intel/haswell
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# Route all USB ports to XHCI per default
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register "xhci_default" = "1"
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013e0000"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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@ -0,0 +1,19 @@
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chip northbridge/intel/haswell
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4)
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register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2)
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register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7)
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5)
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6)
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device domain 0 on
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chip southbridge/intel/lynxpoint
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013e0000"
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end
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end
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end
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@ -1,158 +0,0 @@
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chip northbridge/intel/haswell
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Disable DisplayPort C Hotplug
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register "gpu_dp_c_hotplug" = "0x00"
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# Enable HDMI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM value for eDP
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "400" # 40ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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device lapic 0 on end
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
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register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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chip southbridge/intel/lynxpoint
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "ide_legacy_combined" = "0x0"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x1"
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register "sata_devslp_disable" = "0x1"
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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register "sio_acpi_mode" = "1"
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register "sio_i2c0_voltage" = "0" # 3.3V
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register "sio_i2c1_voltage" = "0" # 3.3V
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# Force enable ASPM for PCIe Port 1
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register "pcie_port_force_aspm" = "0x01"
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# Route all USB ports to XHCI per default
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register "xhci_default" = "1"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on # SMBus
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chip drivers/i2c/rtd2132
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# Panel Power Timings (1 ms units)
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# Note: the panel Tx timings are very
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# different from the LVDS bridge
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# Tx timing settings. Below is a mapping
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# for RTD2132 -> Panel timings.
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# T1 = T2
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# T2 = T8 + T10 + T12
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# T3 = T14
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# T4 = T15
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# T5 = T9 + T11 + T13
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# T6 = T3
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# T7 = T4
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register "t1" = "0x14"
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register "t2" = "0xdc"
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register "t3" = "0x0e"
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register "t4" = "0x02"
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register "t5" = "0xdc"
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register "t6" = "0x14"
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register "t7" = "0x208"
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# LVDS Swap settings are normal.
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register "lvds_swap" = "0"
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# Enable Spread Sprectrum at 0.5%
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register "sscg_percent" = "0x05"
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device i2c 35 on end # (8bit address: 0x6A)
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end # rtd2132
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end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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end
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@ -0,0 +1,54 @@
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chip northbridge/intel/haswell
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "400" # 40ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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device domain 0 on
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chip southbridge/intel/lynxpoint
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register "sata_devslp_disable" = "0x1"
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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device pci 1f.3 on # SMBus
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chip drivers/i2c/rtd2132
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# Panel Power Timings (1 ms units)
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# Note: the panel Tx timings are very
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# different from the LVDS bridge
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# Tx timing settings. Below is a mapping
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# for RTD2132 -> Panel timings.
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# T1 = T2
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# T2 = T8 + T10 + T12
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# T3 = T14
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# T4 = T15
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# T5 = T9 + T11 + T13
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# T6 = T3
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# T7 = T4
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register "t1" = "0x14"
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register "t2" = "0xdc"
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register "t3" = "0x0e"
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register "t4" = "0x02"
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register "t5" = "0xdc"
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register "t6" = "0x14"
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register "t7" = "0x208"
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# LVDS Swap settings are normal.
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register "lvds_swap" = "0"
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# Enable Spread Sprectrum at 0.5%
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register "sscg_percent" = "0x05"
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device i2c 35 on end # (8bit address: 0x6A)
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end # rtd2132
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end # SMBus
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end
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end
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end
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@ -1,130 +0,0 @@
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chip northbridge/intel/haswell
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Disable DisplayPort C Hotplug
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register "gpu_dp_c_hotplug" = "0x00"
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# Enable HDMI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM value for eDP
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register "gpu_pch_backlight_pwm_hz" = "200"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "400" # 40ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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device cpu_cluster 0 on
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chip cpu/intel/haswell
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device lapic 0 on end
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
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register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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chip southbridge/intel/lynxpoint
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "ide_legacy_combined" = "0x0"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x1"
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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register "sio_acpi_mode" = "1"
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register "sio_i2c0_voltage" = "0" # 3.3V
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register "sio_i2c1_voltage" = "0" # 3.3V
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# Force enable ASPM for PCIe Port1
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register "pcie_port_force_aspm" = "0x01"
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# Route all USB ports to XHCI per default
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register "xhci_default" = "1"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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end
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@ -0,0 +1,23 @@
|
|||
chip northbridge/intel/haswell
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
register "gpu_panel_power_cycle_delay" = "5" # 400ms
|
||||
register "gpu_panel_power_up_delay" = "400" # 40ms
|
||||
register "gpu_panel_power_down_delay" = "150" # 15ms
|
||||
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
|
||||
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
|
||||
|
||||
device domain 0 on
|
||||
|
||||
chip southbridge/intel/lynxpoint
|
||||
|
||||
# DTLE DATA / EDGE values
|
||||
register "sata_port0_gen3_dtle" = "0x5"
|
||||
register "sata_port1_gen3_dtle" = "0x5"
|
||||
|
||||
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x013c0000"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
chip northbridge/intel/haswell
|
||||
# IGD Displays
|
||||
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
||||
|
||||
# Enable eDP Hotplug with 6ms pulse
|
||||
register "gpu_dp_d_hotplug" = "0x06"
|
||||
|
||||
# Disable DisplayPort C Hotplug
|
||||
register "gpu_dp_c_hotplug" = "0x00"
|
||||
|
||||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM value for eDP
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12)
|
||||
register "gpu_panel_power_up_delay" = "2000" # 200ms (T3)
|
||||
register "gpu_panel_power_down_delay" = "500" # 50ms (T10)
|
||||
register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8)
|
||||
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9)
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/haswell
|
||||
device lapic 0 on end
|
||||
# Magic APIC ID to locate this chip
|
||||
device lapic 0xACAC off end
|
||||
|
||||
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
|
||||
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
|
||||
|
||||
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
|
||||
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # host bridge
|
||||
device pci 02.0 on end # vga controller
|
||||
device pci 03.0 on end # mini-hd audio
|
||||
|
||||
chip southbridge/intel/lynxpoint
|
||||
register "pirqa_routing" = "0x8b"
|
||||
register "pirqb_routing" = "0x8a"
|
||||
register "pirqc_routing" = "0x8b"
|
||||
register "pirqd_routing" = "0x8b"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x80"
|
||||
|
||||
# EC range is 0x800-0x9ff
|
||||
register "gen1_dec" = "0x00fc0801"
|
||||
register "gen2_dec" = "0x00fc0901"
|
||||
|
||||
# EC_SMI is GPIO34
|
||||
register "alt_gp_smi_en" = "0x0004"
|
||||
register "gpe0_en_1" = "0x00000000"
|
||||
# EC_SCI is GPIO36
|
||||
register "gpe0_en_2" = "0x00000010"
|
||||
register "gpe0_en_3" = "0x00000000"
|
||||
register "gpe0_en_4" = "0x00000000"
|
||||
|
||||
register "ide_legacy_combined" = "0x0"
|
||||
register "sata_ahci" = "0x1"
|
||||
register "sata_port_map" = "0x1"
|
||||
register "sata_devslp_disable" = "0x1"
|
||||
|
||||
# DTLE DATA / EDGE values
|
||||
register "sata_port0_gen3_dtle" = "0x5"
|
||||
register "sata_port1_gen3_dtle" = "0x5"
|
||||
|
||||
register "sio_acpi_mode" = "1"
|
||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||
|
||||
# Force enable ASPM for PCIe Port 1
|
||||
register "pcie_port_force_aspm" = "0x01"
|
||||
|
||||
# Route all USB ports to XHCI per default
|
||||
register "xhci_default" = "1"
|
||||
|
||||
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x013c0000"
|
||||
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 on end # Serial I/O DMA
|
||||
device pci 15.1 on end # I2C0
|
||||
device pci 15.2 on end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 on end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 off end # PCIe Port #3
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 off end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
chip ec/google/chromeec
|
||||
# We only have one init function that
|
||||
# we need to call to initialize the
|
||||
# keyboard part of the EC.
|
||||
device pnp ff.1 on # dummy address
|
||||
end
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
chip northbridge/intel/haswell
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12)
|
||||
register "gpu_panel_power_up_delay" = "2000" # 200ms (T3)
|
||||
register "gpu_panel_power_down_delay" = "500" # 50ms (T10)
|
||||
register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8)
|
||||
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9)
|
||||
|
||||
device domain 0 on
|
||||
|
||||
chip southbridge/intel/lynxpoint
|
||||
|
||||
register "sata_devslp_disable" = "0x1"
|
||||
|
||||
# DTLE DATA / EDGE values
|
||||
register "sata_port0_gen3_dtle" = "0x5"
|
||||
register "sata_port1_gen3_dtle" = "0x5"
|
||||
|
||||
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x013c0000"
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue