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cpu/intel: Remove obsolete comment in CAR setup 

A looong time ago when cache_as_ram.S was built into romstage,
the stage was also linked twice. First at a fixed low address
and then again relocated at the final execute-in-place address.

Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2020-06-13 20:34:54 +03:00 committed by Nico Huber
parent 44ef38f703
commit 61ba7fb2d9
3 changed files with 0 additions and 12 deletions
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4
src/cpu/intel/car/core2/cache_as_ram.S
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@ -132,10 +132,6 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax movl $_program, %eax
andl $_xip_mtrr_mask, %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax

4
src/cpu/intel/car/p3/cache_as_ram.S
View File

@ -121,10 +121,6 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax movl $_program, %eax
andl $_xip_mtrr_mask, %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax

4
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -322,10 +322,6 @@ cache_rom:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax movl $_program, %eax
andl $_xip_mtrr_mask, %eax andl $_xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax