diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 35ab47a1e7..bc9b350f4b 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -43,7 +43,7 @@ struct __packed global_nvs {
 	u8	rsvd2[8];
 
 	/* Base Addresses */
-	u32	cmem; /* 0x30 - CBMEM TOC */
+	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
 	u32	cbmc; /* 0x38 - coreboot memconsole */
 	u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index afeed6f53e..4e2f3ea08b 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -32,7 +32,7 @@ struct __packed global_nvs {
 	u8	s33g; /* 0x15 - Enable 3G in S3 */
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
-	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
+	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
 	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index cc240c5760..bb02cf52ba 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -15,7 +15,7 @@ struct __packed global_nvs {
 	u8	tlvl; /* 0x05 - Throttle Level Limit */
 	u8	lids; /* 0x06 - LID State */
 	u8	pwrs; /* 0x07 - AC Power State */
-	u32	cbmc; /* 0x08 - 0xb AC Power State */
+	u32	cbmc; /* 0x08 - 0xb coreboot Memory Console */
 	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
 	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
 	u8	dpte; /* 0x1c - Enable DPTF */
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 87f16fb5f9..e1b99f2a60 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -31,7 +31,7 @@ struct __packed global_nvs {
 	u8	s33g; /* 0x15 - Enable 3G in S3 */
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
-	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
+	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
 	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */