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AGESA: Fix UMA calculations 

Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.

Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.

Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki 2017-04-15 20:07:53 +03:00
parent 17bb225be7
commit 61be3603f4
15 changed files with 105 additions and 307 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/northbridge/amd/agesa/agesawrapper.c
View File

@ -13,6 +13,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <cbmem.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -110,6 +111,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
status = AmdInitPost(PostParams); status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, &PostParams->StdHeader); AGESA_EVENTLOG(status, &PostParams->StdHeader);
backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;

43
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -422,34 +422,6 @@ static void set_resources(device_t dev)
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
} }
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family12h BKDG. */
/* Please reference MemNGetUmaSizeLN () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size
if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) {
uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */
} else if (sys_mem >= 0x40000000) {
uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
} else {
uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
#endif
}
/* Domain/Root Complex related code */ /* Domain/Root Complex related code */
static void domain_read_resources(device_t dev) static void domain_read_resources(device_t dev)
@ -514,7 +486,6 @@ static void domain_set_resources(device_t dev)
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int idx; int idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -595,8 +566,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, idx, basek, pre_sizek); ram_resource(dev, idx, basek, pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -612,17 +581,10 @@ static void domain_set_resources(device_t dev)
idx += 0x10; idx += 0x10;
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
0, mmio_basek, basek, limitk); 0, mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) if (link->children)
@ -811,11 +773,8 @@ static void root_complex_enable_dev(struct device *dev)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

40
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -458,31 +458,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev); pci_domain_read_resources(dev);
} }
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family14h BKDG. */
sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) {
uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */
}
else {
if (sys_mem >= 0x40000000) {
uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
} else {
uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
}
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
#endif
}
static void domain_set_resources(device_t dev) static void domain_set_resources(device_t dev)
{ {
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
@ -490,7 +465,6 @@ static void domain_set_resources(device_t dev)
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int idx; int idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -576,8 +550,6 @@ static void domain_set_resources(device_t dev)
pre_sizek); pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -594,17 +566,10 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
mmio_basek, basek, limitk); mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
@ -836,11 +801,8 @@ static void root_complex_enable_dev(struct device *dev)
{ {
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

47
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -699,43 +699,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
} }
#endif #endif
#define ONE_MB_SHIFT 20
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
#endif
}
static void domain_set_resources(device_t dev) static void domain_set_resources(device_t dev)
{ {
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int i, idx; int i, idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -806,8 +773,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek); ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -824,16 +789,9 @@ static void domain_set_resources(device_t dev)
idx += 0x10; idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk); i, mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
@ -1095,11 +1053,8 @@ static void root_complex_enable_dev(struct device *dev)
{ {
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

47
src/northbridge/amd/agesa/family15rl/northbridge.c
View File

@ -695,43 +695,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
} }
#endif #endif
#define ONE_MB_SHIFT 20
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
#endif
}
static void domain_set_resources(struct device *dev) static void domain_set_resources(struct device *dev)
{ {
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int i, idx; int i, idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -804,8 +771,6 @@ static void domain_set_resources(struct device *dev)
ram_resource(dev, (idx | i), basek, pre_sizek); ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -823,16 +788,9 @@ static void domain_set_resources(struct device *dev)
idx += 0x10; idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk); i, mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
@ -1085,11 +1043,8 @@ static void root_complex_enable_dev(struct device *dev)
{ {
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

47
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -694,43 +694,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
} }
#endif #endif
#define ONE_MB_SHIFT 20
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
#endif
}
static void domain_set_resources(device_t dev) static void domain_set_resources(device_t dev)
{ {
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int i, idx; int i, idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -801,8 +768,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek); ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -820,16 +785,9 @@ static void domain_set_resources(device_t dev)
idx += 0x10; idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk); i, mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
@ -1082,11 +1040,8 @@ static void root_complex_enable_dev(struct device *dev)
{ {
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

50
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -709,45 +709,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
} }
#endif #endif
#define ONE_MB_SHIFT 20
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
/* refer to UMA Size Consideration in Family16h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */
#endif
}
static void domain_set_resources(device_t dev) static void domain_set_resources(device_t dev)
{ {
unsigned long mmio_basek; unsigned long mmio_basek;
u32 pci_tolm; u32 pci_tolm;
u64 ramtop = 0;
int i, idx; int i, idx;
struct bus *link; struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -806,7 +771,6 @@ static void domain_set_resources(device_t dev)
idx += 0x10; idx += 0x10;
basek = (8*64)+(16*16); basek = (8*64)+(16*16);
sizek = limitk - ((8*64)+(16*16)); sizek = limitk - ((8*64)+(16*16));
} }
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
@ -820,8 +784,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek); ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
if (!ramtop)
ramtop = mmio_basek * 1024;
} }
basek = mmio_basek; basek = mmio_basek;
} }
@ -839,16 +801,9 @@ static void domain_set_resources(device_t dev)
idx += 0x10; idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk); i, mmio_basek, basek, limitk);
if (!ramtop)
ramtop = limitk * 1024;
} }
#if CONFIG_GFXUMA add_uma_resource_below_tolm(dev, 7);
set_top_of_ram(uma_memory_base);
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#else
set_top_of_ram(ramtop);
#endif
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
@ -1101,11 +1056,8 @@ static void root_complex_enable_dev(struct device *dev)
{ {
static int done = 0; static int done = 0;
/* Do not delay UMA setup, as a device on the PCI bus may evaluate
the global uma_memory variables already in its enable function. */
if (!done) { if (!done) {
setup_bsp_ramtop(); setup_bsp_ramtop();
setup_uma_memory();
done = 1; done = 1;
} }

12
src/southbridge/amd/agesa/hudson/ramtop.c
View File

@ -26,27 +26,21 @@ int acpi_get_sleep_type(void)
return (int)tmp; return (int)tmp;
} }
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#ifndef __PRE_RAM__
void backup_top_of_ram(uint64_t ramtop) void backup_top_of_ram(uint64_t ramtop)
{ {
u32 dword = (u32) ramtop; u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */ int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX); outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++; nvram_pos++;
} }
} }
#endif
unsigned long get_top_of_ram(void) unsigned long get_top_of_ram(void)
{ {
uint32_t xdata = 0; uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi; int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi < 4; xi++) { for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX); outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8)); xdata &= ~(0xff << (xi * 8));
@ -55,5 +49,3 @@ unsigned long get_top_of_ram(void)
} }
return (unsigned long) xdata; return (unsigned long) xdata;
} }
#endif

2
src/southbridge/amd/cimx/sb700/Makefile.inc
View File

@ -19,9 +19,11 @@
romstage-y += early.c romstage-y += early.c
romstage-y += smbus.c smbus_spd.c romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c romstage-y += reset.c
romstage-y += ramtop.c
ramstage-y += late.c ramstage-y += late.c
ramstage-y += reset.c ramstage-y += reset.c
ramstage-y += ramtop.c
ramstage-y += smbus.c ramstage-y += smbus.c
ramstage-y += lpc.c ramstage-y += lpc.c

17
src/southbridge/amd/cimx/sb700/lpc.c
View File

@ -20,23 +20,6 @@
#include <console/console.h> /* printk */ #include <console/console.h> /* printk */
#include <cbmem.h> #include <cbmem.h>
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
nvram_pos++;
}
}
#endif
void lpc_read_resources(device_t dev) void lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;

43
src/southbridge/amd/cimx/sb700/ramtop.c Normal file
View File

@ -0,0 +1,43 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <cbmem.h>
#include <southbridge/amd/cimx/cimx_util.h>
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xfc, xi;
for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}

4
src/southbridge/amd/cimx/sb800/Makefile.inc
View File

@ -30,8 +30,8 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c romstage-y += ramtop.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c ramstage-y += ramtop.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c

12
src/southbridge/amd/cimx/sb800/ramtop.c
View File

@ -26,27 +26,21 @@ int acpi_get_sleep_type(void)
return (int)tmp; return (int)tmp;
} }
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#ifndef __PRE_RAM__
void backup_top_of_ram(uint64_t ramtop) void backup_top_of_ram(uint64_t ramtop)
{ {
u32 dword = (u32) ramtop; u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */ int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX); outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++; nvram_pos++;
} }
} }
#endif
unsigned long get_top_of_ram(void) unsigned long get_top_of_ram(void)
{ {
u32 xdata = 0; u32 xdata = 0;
int xnvram_pos = 0xf8, xi; int xnvram_pos = 0xf8, xi;
if (acpi_get_sleep_type() != 3)
return 0;
for (xi = 0; xi < 4; xi++) { for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX); outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8)); xdata &= ~(0xff << (xi * 8));
@ -55,5 +49,3 @@ unsigned long get_top_of_ram(void)
} }
return (unsigned long) xdata; return (unsigned long) xdata;
} }
#endif

2
src/southbridge/amd/cimx/sb900/Makefile.inc
View File

@ -20,11 +20,13 @@ romstage-y += cfg.c
romstage-y += early.c romstage-y += early.c
romstage-y += smbus.c smbus_spd.c romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c romstage-y += reset.c
romstage-y += ramtop.c
ramstage-y += cfg.c ramstage-y += cfg.c
ramstage-y += early.c ramstage-y += early.c
ramstage-y += late.c ramstage-y += late.c
ramstage-y += reset.c ramstage-y += reset.c
ramstage-y += ramtop.c
ramstage-y += smbus.c ramstage-y += smbus.c
ramstage-y += lpc.c ramstage-y += lpc.c

43
src/southbridge/amd/cimx/sb900/ramtop.c Normal file
View File

@ -0,0 +1,43 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <cbmem.h>
#include <southbridge/amd/cimx/cimx_util.h>
void backup_top_of_ram(uint64_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
for (xi = 0; xi < 4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
}