soc/mediatek/mt8195: initialize DFD
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -52,6 +52,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
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ramstage-y += ../common/auxadc.c
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ramstage-y += ../common/ddp.c ddp.c
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ramstage-y += devapc.c
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ramstage-y += ../common/dfd.c
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ramstage-y += ../common/dpm.c
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ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += dpm_4ch.c
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ramstage-y += dp_intf.c dptx.c dptx_hal.c
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8195_DFD_H
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#define SOC_MEDIATEK_MT8195_DFD_H
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#include <soc/dfd_common.h>
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/* DFD dump address and size need to be the same as defined in Kernel DTS. */
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#define DFD_DUMP_ADDRESS 0x6A000000
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#define DFD_DUMP_SIZE (1 * MiB)
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#endif
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@ -1,7 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmem.h>
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#include <device/device.h>
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#include <soc/devapc.h>
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#include <soc/dfd.h>
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#include <soc/emi.h>
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#include <soc/hdmi.h>
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#include <soc/mcupm.h>
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@ -10,6 +12,12 @@
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#include <soc/ufs.h>
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#include <symbols.h>
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void bootmem_platform_add_ranges(void)
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{
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if (CONFIG(MTK_DFD))
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bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED);
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}
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static void soc_read_resources(struct device *dev)
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{
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ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
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@ -21,6 +29,10 @@ static void soc_init(struct device *dev)
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dapc_init();
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mcupm_init();
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sspm_init();
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if (CONFIG(MTK_DFD))
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dfd_init();
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ufs_disable_refclk();
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hdmi_low_power_setting();
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}
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