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soc/amd/cezanne: Add ASYNC_FILE_LOADING 

This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.

BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-11-02 11:51:48 -06:00 committed by Paul Fagerburg
parent 7842755d46
commit 61c9cd9890
1 changed files with 11 additions and 3 deletions
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14
src/soc/amd/cezanne/Kconfig
View File

@ -19,7 +19,6 @@ config SOC_SPECIFIC_OPTIONS
select CPU_INFO_V2 select CPU_INFO_V2
select DRIVERS_USB_ACPI select DRIVERS_USB_ACPI
select DRIVERS_I2C_DESIGNWARE select DRIVERS_I2C_DESIGNWARE
select COOP_MULTITASKING
select DRIVERS_USB_PCI_XHCI select DRIVERS_USB_PCI_XHCI
select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA select FSP_COMPRESS_FSP_S_LZMA
@ -31,7 +30,6 @@ config SOC_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE select IDT_IN_EVERY_STAGE
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PAYLOAD_PRELOAD
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select PROVIDES_ROM_SHARING select PROVIDES_ROM_SHARING
select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
@ -53,7 +51,6 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C
select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_MCAX
select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI
@ -194,6 +191,17 @@ config VERSTAGE_SIZE
Sets the size of DRAM allocation for verstage in linker script if Sets the size of DRAM allocation for verstage in linker script if
running as a separate stage on x86. running as a separate stage on x86.
config ASYNC_FILE_LOADING
bool "Loads files from SPI asynchronously"
select COOP_MULTITASKING
select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
select PAYLOAD_PRELOAD
help
When enabled, the platform will use the LPC SPI DMA controller to
asynchronously load contents from the SPI ROM. This will improve
boot time because the CPUs can be performing useful work while the
SPI contents are being preloaded.
config RAMBASE config RAMBASE
hex hex
default 0x10000000 default 0x10000000