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mb/google/hatch: Support 16MiB fmap 

Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.

BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'

Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Philip Chen 2019-04-05 15:26:13 -07:00 committed by Patrick Georgi
parent 15589b4e56
commit 61d365fafd
3 changed files with 50 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/hatch/Kconfig
View File

@ -1,7 +1,6 @@
config BOARD_GOOGLE_BASEBOARD_HATCH
def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_GENERIC
@ -54,6 +53,11 @@ config DRIVER_TPM_SPI_BUS
config UART_FOR_CONSOLE
default 0
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768
config GBB_HWID
string
depends on CHROMEOS

3
src/mainboard/google/hatch/Kconfig.name
View File

@ -3,14 +3,17 @@ comment "Hatch"
config BOARD_GOOGLE_HATCH
bool "-> Hatch"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_32768
select SOC_INTEL_COMETLAKE
config BOARD_GOOGLE_HATCH_WHL
bool "-> Hatch_whl"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_32768
select SOC_INTEL_WHISKEYLAKE
config BOARD_GOOGLE_KOHAKU
bool "-> Kohaku"
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_COMETLAKE

42
src/mainboard/google/hatch/chromeos-16MiB.fmd Normal file
View File

@ -0,0 +1,42 @@
FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x400000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x3ff000
}
SI_BIOS@0x400000 0xc00000 {
RW_SECTION_A@0x0 0x380000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x36ffc0
RW_FWID_A@0x37ffc0 0x40
}
RW_SECTION_B@0x380000 0x380000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x36ffc0
RW_FWID_B@0x37ffc0 0x40
}
RW_MISC@0x700000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG(PRESERVE)@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x730000 0xd0000
WP_RO@0x800000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x30c000
}
}
}
}