mb/google/hatch: Support 16MiB fmap
Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -1,7 +1,6 @@
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config BOARD_GOOGLE_BASEBOARD_HATCH
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config BOARD_GOOGLE_BASEBOARD_HATCH
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def_bool n
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_GENERIC
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@ -54,6 +53,11 @@ config DRIVER_TPM_SPI_BUS
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config UART_FOR_CONSOLE
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config UART_FOR_CONSOLE
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default 0
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default 0
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768
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config GBB_HWID
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config GBB_HWID
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string
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string
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depends on CHROMEOS
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depends on CHROMEOS
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@ -3,14 +3,17 @@ comment "Hatch"
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config BOARD_GOOGLE_HATCH
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config BOARD_GOOGLE_HATCH
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bool "-> Hatch"
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bool "-> Hatch"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_32768
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select SOC_INTEL_COMETLAKE
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select SOC_INTEL_COMETLAKE
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config BOARD_GOOGLE_HATCH_WHL
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config BOARD_GOOGLE_HATCH_WHL
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bool "-> Hatch_whl"
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bool "-> Hatch_whl"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_32768
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select SOC_INTEL_WHISKEYLAKE
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select SOC_INTEL_WHISKEYLAKE
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config BOARD_GOOGLE_KOHAKU
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config BOARD_GOOGLE_KOHAKU
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bool "-> Kohaku"
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bool "-> Kohaku"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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select SOC_INTEL_COMETLAKE
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select SOC_INTEL_COMETLAKE
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@ -0,0 +1,42 @@
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x3ff000
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}
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SI_BIOS@0x400000 0xc00000 {
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RW_SECTION_A@0x0 0x380000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x36ffc0
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RW_FWID_A@0x37ffc0 0x40
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}
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RW_SECTION_B@0x380000 0x380000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x36ffc0
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RW_FWID_B@0x37ffc0 0x40
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}
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RW_MISC@0x700000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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RW_LEGACY(CBFS)@0x730000 0xd0000
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WP_RO@0x800000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x3fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x30c000
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}
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}
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}
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}
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