From 61dd05e010d91447eafff11cd65baab4e21e0bdb Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Fri, 12 Mar 2021 18:28:03 +0530 Subject: [PATCH] soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstage This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync() must be called after DRAM initialization. Test=Verified on Alderlake platform Signed-off-by: Sridhar Siricilla Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/romstage/romstage.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index cc3126bb41..d7ef14d11f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -129,6 +129,15 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } }