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azalia: Make `set_bits` function non-static 

There's many copies of this function in the tree. Make the copy in
azalia_device.c non-static and rename it to `azalia_set_bits`, then
replace all other copies with it. Since azalia_device.c is only built
when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.

This has the side-effect of building hda_verb.c from the mainboard
directory. If this patch happens to break audio on a mainboard, it's
because its hda_verb.c was always wrong but wasn't being compiled.

Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-12-05 18:02:32 +01:00 committed by Hung-Te Lin
parent c8be0947f1
commit 61dd8365bf
16 changed files with 32 additions and 213 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/device/azalia_device.c
View File

@ -7,7 +7,7 @@
#include <device/mmio.h>
#include <delay.h>
static int set_bits(void *port, u32 mask, u32 val)
int azalia_set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@ -40,7 +40,7 @@ static int codec_detect(u8 *base)
int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
goto no_codec;
/* clear STATESTS bits (BAR + 0xe)[2:0] */
@ -62,11 +62,11 @@ static int codec_detect(u8 *base)
goto no_codec;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@ -80,7 +80,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
return 0;
}

1
src/include/device/azalia_device.h
View File

@ -18,6 +18,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
int azalia_set_bits(void *port, u32 mask, u32 val);
void azalia_audio_init(struct device *dev);
extern struct device_operations default_azalia_audio_ops;

1
src/soc/intel/common/Kconfig.common
View File

@ -1,5 +1,6 @@
config SOC_INTEL_COMMON
bool
select AZALIA_PLUGIN_SUPPORT
select HAVE_DISPLAY_MTRRS
help
common code for Intel SOCs

35
src/soc/intel/common/hda_verb.c
View File

@ -7,39 +7,12 @@
#include "hda_verb.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
int hda_codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@ -51,11 +24,11 @@ int hda_codec_detect(u8 *base)
write8(base + HDA_STATESTS_REG, 0xf);
/* Turn off the link and poll RESET# bit until it reads back as 0 */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
goto no_codec;
/* Turn on the link and poll RESET# bit until it reads back as 1 */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
@ -69,7 +42,7 @@ int hda_codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}

1
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -11,6 +11,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS

31
src/southbridge/intel/bd82x6x/azalia.c
View File

@ -14,39 +14,12 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@ -63,7 +36,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}

1
src/southbridge/intel/i82801gx/Kconfig
View File

@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801GX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER

33
src/southbridge/intel/i82801gx/azalia.c
View File

@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801gx.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}

1
src/southbridge/intel/i82801ix/Kconfig
View File

@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801IX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select HAVE_SMI_HANDLER if !NO_SMM
select HAVE_USBDEBUG_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE

33
src/southbridge/intel/i82801ix/azalia.c
View File

@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801ix.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}

1
src/southbridge/intel/i82801jx/Kconfig
View File

@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801JX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select HAVE_SMI_HANDLER

33
src/southbridge/intel/i82801jx/azalia.c
View File

@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801jx.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}

1
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT

31
src/southbridge/intel/ibexpeak/azalia.c
View File

@ -10,39 +10,12 @@
#include <device/azalia_device.h>
#include "pch.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@ -59,7 +32,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}

1
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9

31
src/southbridge/intel/lynxpoint/hda_verb.c
View File

@ -8,39 +8,12 @@
#include "pch.h"
#include "hda_verb.h"
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was just written to it */
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
int hda_codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@ -57,7 +30,7 @@ int hda_codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}