mb/google/rex: Add WWAN ACPI support
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. BUG=b:244077118 TEST=check cbmem -c \_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3) \_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL) check PXSX Device is generated in ssdt. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -23,6 +23,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
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def_bool n
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def_bool n
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select BOARD_GOOGLE_REX_COMMON
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select BOARD_GOOGLE_REX_COMMON
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_PMC
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select DRIVERS_WWAN_FM350GL
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_CHROMEOS
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select MEMORY_SOLDERDOWN
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_METEORLAKE
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select SOC_INTEL_METEORLAKE
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@ -265,6 +265,23 @@ chip soc/intel/meteorlake
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.clk_req = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
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register "reset_off_delay_ms" = "20"
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register "srcclk_pin" = "3"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)"
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 on end
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end
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end #PCIE6 WWAN card
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end #PCIE6 WWAN card
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device ref gspi1 on end
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device ref gspi1 on end
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device ref soc_espi on
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device ref soc_espi on
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