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mb/google/rex: Add WWAN ACPI support 

Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.

BUG=b:244077118
TEST=check cbmem -c
\_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3)
\_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL)

check PXSX Device is generated in ssdt.

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ivy Jian 2022-09-05 14:30:11 +08:00 committed by Martin Roth
parent d4eb998fc1
commit 61e5816b26
2 changed files with 18 additions and 0 deletions
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1
src/mainboard/google/rex/Kconfig
View File

@ -23,6 +23,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
def_bool n
select BOARD_GOOGLE_REX_COMMON
select DRIVERS_INTEL_PMC
select DRIVERS_WWAN_FM350GL
select MAINBOARD_HAS_CHROMEOS
select MEMORY_SOLDERDOWN
select SOC_INTEL_METEORLAKE

17
src/mainboard/google/rex/variants/rex0/overridetree.cb
View File

@ -265,6 +265,23 @@ chip soc/intel/meteorlake
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "3"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
device generic 0 alias rp6_rtd3 on end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "add_acpi_dma_property" = "true"
use rp6_rtd3 as rtd3dev
device generic 0 on end
end
end #PCIE6 WWAN card
device ref gspi1 on end
device ref soc_espi on