GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mediatek/mt8183: Add DDR driver of rx datlat calibration part 

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28843
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Huayang Duan 2018-09-26 17:50:44 +08:00 committed by Patrick Georgi
parent 0afc41e865
commit 6202d1b51a
1 changed files with 72 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
View File

@ -1624,6 +1624,75 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank,
return 0; return 0;
} }
static void dle_factor_handler(u8 chn, u8 val)
{
val = MAX(val, 2);
clrsetbits_le32(&ch[chn].ao.shu[0].conf[1],
SHU_CONF1_DATLAT_MASK | SHU_CONF1_DATLAT_DSEL_MASK |
SHU_CONF1_DATLAT_DSEL_PHY_MASK,
(val << SHU_CONF1_DATLAT_SHIFT) |
((val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) |
((val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT));
dram_phy_reset(chn);
}
static u8 dramc_rx_datlat_cal(u8 chn, u8 rank)
{
s32 datlat, first = -1, sum = 0, best_step;
best_step = read32(&ch[chn].ao.shu[0].conf[1]) & SHU_CONF1_DATLAT_MASK;
dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: %2x\n",
chn, rank, best_step);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd);
dramc_engine2_init(chn, rank, 0x400, false);
for (datlat = 12; datlat < DATLAT_TAP_NUMBER; datlat++) {
dle_factor_handler(chn, datlat);
u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK);
if (err != 0 && first != -1)
break;
if (sum >= 4)
break;
if (err == 0) {
if (first == -1)
first = datlat;
sum++;
}
dramc_dbg("Datlat=%2d, err_value=0x%8x, sum=%d\n",
datlat, err, sum);
}
dramc_engine2_end(chn);
write32(&ch[chn].ao.dummy_rd, dummy_rd_backup);
best_step = first + (sum >> 1);
dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n",
first, sum, best_step);
assert(sum != 0);
dle_factor_handler(chn, best_step);
clrsetbits_le32(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND_MASK,
(0x1 << PADCTRL_DQIENQKEND_SHIFT) |
(0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT));
return (u8) best_step;
}
static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 datlat0, u8 datlat1)
{
u8 final_datlat = MAX(datlat0, datlat1);
dle_factor_handler(chn, final_datlat);
}
static void dramc_rx_dqs_gating_post_process(u8 chn) static void dramc_rx_dqs_gating_post_process(u8 chn)
{ {
u8 rank_rx_dvs, dqsinctl; u8 rank_rx_dvs, dqsinctl;
@ -1720,6 +1789,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn)
void dramc_calibrate_all_channels(const struct sdram_params *pams) void dramc_calibrate_all_channels(const struct sdram_params *pams)
{ {
u8 rx_datlat[RANK_MAX] = {0};
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
dramc_show("Start K ch:%d, rank:%d\n", chn, rk); dramc_show("Start K ch:%d, rank:%d\n", chn, rk);
@ -1731,9 +1801,11 @@ void dramc_calibrate_all_channels(const struct sdram_params *pams)
dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams);
dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams);
dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams);
rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk);
dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams);
} }
dramc_rx_dqs_gating_post_process(chn); dramc_rx_dqs_gating_post_process(chn);
dramc_dual_rank_rx_datlat_cal(chn, rx_datlat[0], rx_datlat[1]);
} }
} }