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AMD SB800 southbridge update 

This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.

Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kerry She 2011-08-18 18:44:00 +08:00 committed by Stefan Reinauer
parent feed329a0c
commit 6209c8299a
10 changed files with 45 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/advansus/a785e-i/Kconfig
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@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF #COM1, COM2
#select SUPERIO_FINTEK_F81216AD #COM3, COM4
select SB_SUPERIO_HWM
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE

5
src/mainboard/advansus/a785e-i/platform_cfg.h
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@ -219,4 +219,9 @@
*/
#define GEC_CONFIG 0
/**
* @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
*/
#define SIO_HWM_BASE_ADDRESS 0x290
#endif

1
src/mainboard/asrock/e350m1/Kconfig
View File

@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF
select SB_SUPERIO_HWM
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE

5
src/mainboard/asrock/e350m1/platform_cfg.h
View File

@ -219,4 +219,9 @@
*/
#define GEC_CONFIG 0
/**
* @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
*/
#define SIO_HWM_BASE_ADDRESS 0x290
#endif

4
src/southbridge/amd/cimx/sb800/Kconfig
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@ -27,5 +27,9 @@ if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/cimx/sb800/bootblock.c"
config SB_SUPERIO_HWM
bool
default n
endif #SOUTHBRIDGE_AMD_CIMX_SB800

1
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
View File

@ -120,6 +120,7 @@ typedef union _PCI_ADDR {
#define cimIrConfigDefault 0x00 // Disable
#define cimSpiFastReadEnableDefault 0x01 // Enable
#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
#define cimSioHwmPortEnableDefault FALSE
// GPP/AB Controller
#define cimNbSbGen2Default TRUE
#define cimAlinkPhyPllPowerDownDefault TRUE

5
src/southbridge/amd/cimx/sb800/cfg.c
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@ -50,6 +50,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS;
sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
@ -94,6 +95,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
/* LPC */
/* SuperIO hardware monitor register access */
sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
/*
* GPP. default configure only enable port0 with 4 lanes,
* configure in devicetree.cb would overwrite the default configuration

8
src/vendorcode/amd/cimx/sb800/OEM.h
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@ -86,6 +86,14 @@
#define SIO_PME_BASE_ADDRESS 0xE00
#endif
/**
* SIO_HWM_BASE_ADDRESS - Super IO HWM base address
*
*/
#ifndef SIO_HWM_BASE_ADDRESS
#define SIO_HWM_BASE_ADDRESS 0x290
#endif
/**
* SPI_BASE_ADDRESS - SPI controller (ROM) base address
*

11
src/vendorcode/amd/cimx/sb800/SBPOR.c
View File

@ -144,6 +144,7 @@ sbPowerOnInit (
UINT8 cimSataMode;
UINT8 cimSpiFastReadEnable;
UINT8 cimSpiFastReadSpeed;
UINT8 cimSioHwmPortEnable;
UINT8 SataPortNum;
cimNbSbGen2 = pConfig->NbSbGen2;
@ -155,12 +156,14 @@ sbPowerOnInit (
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
}
cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
#if SB_CIMx_PARAMETER == 0
cimNbSbGen2 = cimNbSbGen2Default;
cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
#endif
// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
@ -200,6 +203,12 @@ sbPowerOnInit (
// Set Build option into SB
WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
if (cimSioHwmPortEnable) {
// Use Wide IO Port 1 to provide access to the superio HWM registers.
WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
}
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
@ -354,4 +363,4 @@ sbPowerOnInit (
// Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
}
}

5
src/vendorcode/amd/cimx/sb800/SBTYPE.h
View File

@ -156,6 +156,10 @@ typedef struct _BUILDPARAM {
* @par
* SIO PME BASE Address
*/
unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress
* @par
* SIO HWM BASE Address
*/
unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
* @par
* Watch Dog Timer Address
@ -911,6 +915,7 @@ typedef struct _AMDSBCFG {
unsigned int MTC1e:1; //29
/** MiscDummy - Reserved */
unsigned int MiscDummy:2; //31:30
unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
//DebugOptions //offset 4 bytes (146-149)
/** PcibAutoClkCtrlLow - Debug function Reserved */