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mb/google/brya/variants/primus: update USB 2.0 controller Lane Parameter 

Modify USB 2.0 port5 parameter to improve SI diagram measurement.

BUG=b:187992881
TEST= Pass USB 2.0 SI Eye diagram measurement.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1eff05a7ad6563898744c24f9657e28625319873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Casper Chang 2021-08-27 16:34:03 +08:00 committed by Felix Held
parent 0d753e5108
commit 621ae7c701
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brya/variants/primus/overridetree.cb
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@ -60,6 +60,7 @@ chip soc/intel/alderlake
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
register "usb3_ports[2]" = "USB3_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
device domain 0 on
device ref dtt on